A5044005800- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Integrated Circuits and Semiconductor Failure Analysis
- Nanowire Synthesis and Applications
- Thin-Film Transistor Technologies
- Photonic and Optical Devices
- Advanced Memory and Neural Computing
- Semiconductor materials and interfaces
- Advanced Data Storage Technologies
- Copper Interconnects and Reliability
- 3D IC and TSV technologies
- Silicon Carbide Semiconductor Technologies
- Semiconductor Lasers and Optical Devices
- Electronic and Structural Properties of Oxides
- Semiconductor Quantum Structures and Devices
- VLSI and Analog Circuit Testing
- Silicon and Solar Cell Technologies
- Chalcogenide Semiconductor Thin Films
- Advanced Fiber Optic Sensors
- Advanced Electron Microscopy Techniques and Applications
- Parallel Computing and Optimization Techniques
- Advanced Photonic Communication Systems
- GaN-based semiconductor devices and materials
- Ga2O3 and related materials
IMEC
2013-2024
KU Leuven
2015-2017
We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A CFET process is cost effective compared to a sequential process. The small N/P separation in results lower parasitics and higher performance gains. In this paper, fabrication flow, we demonstrate functional PMOS FinFET bottom devices NMOS nanosheet FET top devices. Process development all critical modules enable these are presented. Monolithic scheme...
This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: Q factor increased to 25 as compared our previous work, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> = 500 μA/ μm at xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> 100 nA/μm achieved, approaching best...
Full channel and Macaroni-type 3-D SONOS memories are thoroughly compared. Macaroni provides easier device controllability, resulting in tighter distributions of all electrical characteristics, at the expense lower conduction. Next to this clear trade-off, memory window is also degraded. Improving material quality way alleviate as demonstrated by Laser Thermal Anneal treatment channel.
Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, first time, integration of tungsten (W) BPR lines with Si finFETs. technology requires insertion metal in front-end-of-line (FEOL) stack. poses risks stack deformation and device degradation due to metal-induced stress contamination. To assess deformation, we demonstrate W-BPR which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting...
We have demonstrated that the engineering of Si channel grains in vertical 3D devices is tremendous importance for read current, leading to up 10 times higher ID, 3 steeper STS slope, tighter ID and distributions, better channel-oxide interface, less defective grain boundaries larger memory window. LTA arises as a potential candidate engineer microstructure. The limitations regarding crystallization depth can be overcome through complementary techniques such substrate heating assisted LTA....
In this paper, Epi-Si process is used to investigate the impact of traps and grain boundaries in vertical 3D NAND. With channel morphology, we show that defects have a reduced on device performances compared usual poly-Si devices. These results are also confirmed extrapolated other geometry using TCAD simulations.
Nanowires (NW) and nanosheets (NS) are promising channel structure for future technology nodes as they can offer better electrostatics than FinFETs. In this paper, we show another advantage of strained Ge NW pFET over FinFET, which lies in the preservation Strain-Relaxed-Buffer (SRB)-induced strain through fin cut S/D recess. This benefit comes from presence sacrificial SiGe layers. Lowering concentration layer is a way to further suppress loss. Furthermore, comparison pFETs integrated on...
Epitaxially grown In1−xGaxAs is integrated for the first time as replacement of polycrystalline silicon (Si) channel down to 45 nm diameter 3-D NAND memory application. Channels with different compositions are obtained after careful surface preparation by tuning growth conditions such as: temperature, choice precursors and flow ratio. shows superior conduction properties than poly-Si channel: higher Ion transconductance (gm). Potentially good operations also found.
The characterization of vertical poly-Si transistors, important for optimizing SONOS memory configurations, is studied by means a resistive network model. statistical variation the I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</inf> -V xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> characteristics allows to extract grain size and from sub-threshold regime information on energy distribution defects extracted. This model indicates...
An in-depth study of scaled nanowire Ge pFETs for digital and analog applications is proposed. Improved device characteristics are first obtained after gaining a good understanding the HPA on performance. Up to 45% higher ID,SAT at I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> =3nA/fin when comparing best Si GAA nFET similar found benchmarking mature 14/16nm pFinFET technology -0.5 V...
We report on production compatible low temperature (≤320 °C) selective epitaxial growth schemes for boron doped Ge0.99Sn0.01 and Ge in source/drain areas of FinFET gate-all-around (GAA) strained-Ge pMOS transistors. Active B concentrations are as high 3.2 × 1020 cm−3 2.2 Ge, respectively. The Ge:B is based a cyclic deposition etch approach using Cl2 an etchant, while the Ge0.99Sn0.01:B nature. Low Ti/p+ Ge(Sn):B contact resistivities 3.6 10−9 Ω cm2 (Ge0.99Sn0.01) 5.5 (Ge:B) have been...
Epitaxially grown Si and <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.6</sub> Ge xmlns:xlink="http://www.w3.org/1999/xlink">0.4</sub> are integrated as replacement of poly-Si channel in vertical cylindrical transistors for NAND memory application, order to investigate the impact grain boundaries on current conduction. Epi-Si outperforms both Epi-SiGe channels, resulting best conduction, with large improvement sub threshold swing...
Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, first time, integration of tungsten (W) BPR lines with Si finFETs. The characteristics in close proximity to floating are found be similar without BPR. Moreover, W-BPR interface Ru via contact can withstand more than 320 h electromigration (EM) stress at 4 MA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 330°C,...
This paper demonstrates high performance strained p-type double stacked Ge Gate-AlI-Around (GAA) devices at significantly reduced gate lengths (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ~ 25nm) compared to our previous work. Excellent electrostatic control is maintained down L =25 nm by using extension-less scheme, while the kept appropriate spacer scaling and implementation of highly B-doped or GeSn as source/drain (S/D) material.
We have demonstrated Ge nFinFETs with a record high GmSAΓ/SSSAT and PBTI reliability by improving the RMG high-k last process. The SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dummy gate oxide (DGO) deposition removal processes been identified as knobs to improve electron mobility even nominally identical Si-passivated stack. Surface oxidation of channel during DGO is considered impact final By suppressing surface oxidation,...
Epitaxial In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> Ga xmlns:xlink="http://www.w3.org/1999/xlink">1–<i>x</i></sub> As is grown by metal organic vapor phase epitaxy as replacement of polycrystalline silicon (Si) channel for high-density 3-D NAND memory applications. The most challenging steps to integrate are thoroughly discussed; their impact on the electrical performances investigated and tunnel oxide (TuOx) quality...
This paper describes our recent research progress on high-mobility Ge-channel n/pFETs. Gate stack, junction and contact are the key challenging components of Ge Through improvement those unit modules, electrical performance reliability FinFET gate-all-around (GAA) nanowire (NW) pFETs have been improved. Remaining technical challenges for realization high reliable n/pFETs will be discussed.
Abstract We propose for the first time a dedicated FinFET technology with specific optimization tox >40 nm and lateral breakdown >35 V to replace conventional planar high voltage transistors in 3D NAND Flash periphery. show significant current increase (> x 2) area saving per footprint, solving one of key bottlenecks future nodes. Fabrication thermally stable prototypes is shown, no impact on overall fabrication complexity.
This paper reports on strained p-type Ge Gate-All-Around (GAA) devices 300mm SiGe Strain-Relaxed-Buffers (SRB) with improved performance as compared to our previous work. The Q factor is increased 25, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> =500μA/μm at xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> =100nA/μm achieved, approaching the best published results finFETs. Good NBTI reliability also maintained. By using process...
We demonstrate multiple ways to reduce the D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> of Si-cap-free low-Ge-content (25-30%) SiGe gate stack. The is reduced by i) Ge oxide scavenging via condensation or work function metal (WFM), ii) nitridation dielectrics and iii) optimized high-pressure anneal (HPA). A moderate interface layer (IL) beneficial in EOT reduction, while HfO xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>...
Vertically stacked gate-all-around nanowires (GAA NWs) are considered a promising architecture for ultimately scaled complementary metal oxide semiconductor devices. These the natural evolution of fin-shaped field effect transistor (finFET) design and enable better electrostatic control higher drive current per footprint w.r.t. previous architectures. Transmission electron microscopy (TEM) analysis is employed in development stages these devices to investigate morphology, material diffusion,...
Hot-carrier degradation (HCD) of Ge pNWFETs has been shown to be significantly lower and different than that Si pNWFETs. Here we accurately model the time-to-failure (TTF) measured during HC stress in For this, use our HCD framework validated against hot-carrier devices, first show here it thoroughly represents This is naturally extendable incorporate new defects (O-vacancies) their precursors (Ge-O bonds) which are involved transistors. These Ge-O bonds present due segregation through cap...
This paper shows the importance of oxygen control at SiGe fin surface and within gate stack. Optimized SiN liners are required to protect fins from oxidation during a flowable CVD (FCVD) densification anneal. Suppression diffusion or scavenging GeO via metal electrode is essential achieve low-D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> By replacing HfO xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> with other dielectrics...
Abstract Automotive, Artificial Intelligence/Machine Learning and blockchain generation are imposing increasing demanding specs for Dynamic Random Access Memory (DRAM) memories. Wider memory bandwidth can be achieved by using conventional planar SiO 2 MOSFET different interfaces but at the expense of required energy per bit. Advantages High-K/Metal Gate versus /SiON DRAM periphery devices compatible with fabrication have been demonstrated in literature. More recently, power performance...
In this study, we explored the key properties and functionalities of plasma enhanced atomic layer deposition (PEALD) SiNx films, synthesized using different temperatures (500–550 °C) conditions (lower higher), both on 300 mm blanket Si several integrated 3D topology substrates, at thicknesses relevant for diverse nanoscale applications. Our study shows that with an increase temperature °C), a small reduction in HF wet etch rate (1.1–0.69 nm/min), H content (9.6% vs 7.4%) was observed. When...