A5039544876- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Integrated Circuits and Semiconductor Failure Analysis
- Copper Interconnects and Reliability
- Semiconductor materials and interfaces
- 3D IC and TSV technologies
- Thin-Film Transistor Technologies
- Low-power high-performance VLSI design
- Electronic and Structural Properties of Oxides
- Nanowire Synthesis and Applications
- Metal and Thin Film Mechanics
- Electrical Contact Performance and Analysis
- Silicon and Solar Cell Technologies
- Graphene research and applications
- Electrostatic Discharge in Electronics
- Quantum and electron transport phenomena
- Electronic Packaging and Soldering Technologies
- VLSI and Analog Circuit Testing
- Silicon Carbide Semiconductor Technologies
- 2D Materials and Applications
- Advanced Memory and Neural Computing
- Parallel Computing and Optimization Techniques
- Electron and X-Ray Spectroscopy Techniques
- Silicon Nanostructures and Photoluminescence
IMEC
2017-2024
Angstrom Designs (United States)
2023
Analog Devices (United States)
2023
Universität der Bundeswehr München
2023
Shanghai Institute for Science of Science
2023
Victoria University of Bangladesh
2023
MIT World Peace University
2023
National Taiwan University
2023
KU Leuven
2020
Coventor (France)
2020
We report on CMOS-integrated vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFETs with in-situ doped source-drain stressors and dual work function metal gates. demonstrate that oxidation-induced SiGe/Si fin deformation by STI densification is effectively suppressed a SiN liner. This protection improves the controllability of formation. In addition, highly-selective nano-wire release inner spacer cavity formation without re-flow are demonstrated. Finally, for first time we...
To compensate for expected gate pitch scaling slowdown below 42nm, several boosters are needed to reduce the logic standard cell height (CH). However, limited benefits can be achieved using FinFET and Gate all around (GAA) nanosheets (NSHs) due integration limits in achieving tight PMOS NMOS (PN) separation. Therefore, a novel forksheet (FSH) device architecture is proposed extremely scaled PN space additional processing complexity. The FSH achieves 10% frequency increase at iso-power 24%...
We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A CFET process is cost effective compared to a sequential process. The small N/P separation in results lower parasitics and higher performance gains. In this paper, fabrication flow, we demonstrate functional PMOS FinFET bottom devices NMOS nanosheet FET top devices. Process development all critical modules enable these are presented. Monolithic scheme...
This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: Q factor increased to 25 as compared our previous work, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> = 500 μA/ μm at xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> 100 nA/μm achieved, approaching best...
Vertical graphene-based device concepts that rely on quantum mechanical tunneling are intensely being discussed in literature for applications electronics and optoelectronics. In this work, the carrier transport mechanisms semiconductor-insulator-graphene (SIG) capacitors investigated with respect to their suitability as electron emitter vertical graphene base transistors (GBTs). Several dielectric materials tunnel barriers compared, including double layers. Using bilayer dielectrics, we...
We report on Si nanosheet monolithic Complementary Field-Effect Transistors (CFETs) at industry-relevant 48nm gate pitch, with source-drains (SDs) and SD contacts formed for either bottom or top devices. epi patterning 30nm vertical N-P space high-aspect-ratio contact formation are successfully demonstrated. Functional devices excellent subthreshold slope $(SS_{SAT}=7075$ mV/dec) reported devices, both N- PMOS. Middle dielectric isolation (MDI) by SiGe replacement processing is introduced as...
Forksheet devices have been recently proposed to further reduce the n-to-p spacing/footprint of transistors on wafer. In this work, we report a systematic comparison DC performance Forksheets and Nanosheets (with relevant dimensions 23nm width 7nm thickness) co-integrated same wafers. It is shown that short channel control transport properties (from Room Temperature up 125°C) are comparable down LG=22nm. We also show gate stack reliability does not suffer from SiN deposition etch back...
Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, first time, integration of tungsten (W) BPR lines with Si finFETs. technology requires insertion metal in front-end-of-line (FEOL) stack. poses risks stack deformation and device degradation due to metal-induced stress contamination. To assess deformation, we demonstrate W-BPR which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting...
We report on nanosheet (NS) FETs as promising candidates to replace finFETs and continue delivering profitable node scaling gains. Key fabrication challenges addressed here include device parasitics' reduction via inner spacers integration channels' stress control. Further options may involve evolution into a forksheet (FS) type of configuration with shrunk p-n spacing, and/or stacking different polarity devices single 3D structure. Lastly, by fully exploring the third dimension, vertical NS...
We report on forksheet field-effect transistors that are isolated from the substrate by bottom dielectric isolation (BDI) formed replacing a SiGe epitaxial layer with film while devices anchored to walls. Functional unipolar BDI demonstrated for both N- and PMOS, wall widths down 10 nm. In addition, we describe scheme isolate adjacent source-drain structures wall. This relies increasing height, means of active area patterning hard mask engineering, compensate losses in downstream process...
Interfacial layer (IL) control in high-k/metal gate stacks is crucial achieving good interface quality, mobility, and reliability. A process developed for the formation of a thulium silicate IL that can be integrated as replacement conventional chemical oxide ILs gate-last CMOS process. straightforward integration scheme demonstrated, based on self-limiting inert gas atmosphere with selectivity etching step. The shown to provide <formula formulatype="inline"...
The increased metal resistance degrades both the performance and write margin of SRAM circuits in sub-10nm nodes. This paper utilizes buried power distribution as ability booster 3nm node. BPR-SRAM offers up to 34.5% read speed 498.6mV improvement over conventional SRAM. Gem5 system simulator predicts 28.2% gain with server-processor having L2 L3 cache compared baseline.
This work reports metal exploration for buried power rail (BPR) and Via-to-BPR (VBPR) towards the 1 nm node. For tungsten, which is first choice of BPR at 3 node, we optimize W metallization stack to minimize line resistivity, together with ways reduce W-BPR - W-VBPR contact resistance (R). scaled CDs 2 nodes, introduce molybdenum level benchmark its R electromigration against Ru metallization. Additionally, Mo dry & wet, selective etch processes enable Mo-BPR recess in fin/STI fin pitch 24...
We report on scaled finFETs built with a novel routing scheme wherein devices are connected via buried power rails (BPRs) from both wafer sides, tight variability and matching control. On the wafer's frontside (FS), M1 lines (FSM1) through V0 vias to M0A which then linked BPR by called VBPR while also contacting directly device's S/D-epi. As for gate wiring, enable in this work its access is landing it neighboring line set only field-oxide. A single-step metallization preceded situ...
A novel process for atomic layer deposition of thulium oxide (Tm2O3) has been developed, employing TmCp3 as metal precursor and H2O oxidizing agent. The use a highly reactive organometallic eliminates the need strong agent (such O3) provides high rate ∼1.5 Å/cycle. thorough characterization performed, identifying true ALD-type film growth in temperature range 200–300°C. ALD further investigated by extensive physical electrical deposited films terms composition, crystalline phase, surface...
Integration of a high-k interfacial layer (IL) is promising technological solution to improve the scalability /metal gate CMOS technology. We have previously demonstrated CMOS-compatible integration scheme for thulium silicate (TmSiO) IL and shown excellent characteristics in terms equivalent oxide thickness (EOT), interface state density, channel mobility, threshold voltage control. Here, we report on optimized annealing conditions leading leakage current density comparable with...
A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. model a FinFET was built using virtual and testing. The subsequently calibrated Design Experiment corner case data that had been collected limited number processed fab wafers. We then performed 400 experiments comprising seven sources variation. Using this technique, we were able identify minimum gate-to-source/drain spacer...
Continued scaling of DRAM technologies has required a limitation the power dissipation from logic components on-chip, while downscaling both transistor oxide thickness and gate length. One route to enable further scaling, circumventing excessive leakage currents, is integration high-permittivity (κ) metal-gate (HKMG) into high-voltage (e.g., I/O) devices. The requirement gate-first flow for devices in peripheral region introduces significant reliability challenges. Even though Negative Bias...
Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, first time, integration of tungsten (W) BPR lines with Si finFETs. The characteristics in close proximity to floating are found be similar without BPR. Moreover, W-BPR interface Ru via contact can withstand more than 320 h electromigration (EM) stress at 4 MA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 330°C,...
This paper reports BPR/Via-to-BPR (VBPR) module development at 24nm fin pitch (FP) / 42nm contacted gate (CPP), and W Ru-BPR Ru- Contact-to-Active (M0A)/VBPR resistance (R) & electromigration (EM). BPR dielectric barrier, plug reveal are optimized to enable scaling. A self-aligned VBPR etch is also demonstrated by Q-ALE process. meets line R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">target</sub> <; 50 Ω/μm ~2× smaller aspect ratio than...
Dipole- first gate stack is demonstrated as a scalable, thermal budget flexible and wide/fine-tunable multi- Vt solution for 3D integrated gate-all-around nanosheet devices. Whereas dipole-forming shifter deposited on high-k in "dipole-last" scheme, the directly SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> interface layer (IL) "dipole-first". This enables to (1) reduce of process (2) provide larger shift than dipole-last scheme....
3D sequential stacking is demonstrated using top tier FDSOI devices on bottom bulk finFETs. integration and top-bottom layer interconnectivity validated through functional via chains, CMOS single inverters inverter chain with transistors built in the layers. Three different Si transfer flows, including a low temperature Smart Cut™, are investigated compared electrically for planar devices. Transfer of bi-axial tensile strained silicon 60-80% performance boost nMOS device over unstrained...
We evaluate the reliability of barrierless Mo metallization on various dielectrics that are used in both BEOL and MOL integration schemes. In particular, we assess risk metal drift-induced failure SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , LK3.0, SiCO Si xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> N xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> films by performing TDDB measurements MIM planar capacitors. show does...