A5065901381- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Silicon Carbide Semiconductor Technologies
- Semiconductor materials and interfaces
- Electrostatic Discharge in Electronics
- Thin-Film Transistor Technologies
- Silicon and Solar Cell Technologies
- Advanced Memory and Neural Computing
- Catalytic Processes in Materials Science
- MXene and MAX Phase Materials
- Copper Interconnects and Reliability
- Nanowire Synthesis and Applications
- SARS-CoV-2 and COVID-19 Research
- Diverse Scientific Research Studies
- COVID-19 Clinical Research Studies
- Advanced Chemical Physics Studies
- Low-power high-performance VLSI design
- Ga2O3 and related materials
- 2D Materials and Applications
- Electrocatalysts for Energy Conversion
- Health and Well-being Studies
- Catalysis and Oxidation Reactions
- Radiation Effects in Electronics
Intel (United States)
2025
Indian Institute of Technology Bombay
2016-2023
IMEC
2020-2022
Patanjali Research Foundation
2022
East Asia School of Theology
2021
Indian Institute of Technology Gandhinagar
2016
A comprehensive modeling framework is presented to predict the time kinetics of negative bias temperature instability stress and recovery during after dc ac stresses also mixed dc-ac stress. The model uses uncorrelated contributions from generation interface bulk traps hole trapping in preexisting traps. Ultrafast measured data at different biases, temperature, duty cycle frequency, as well arbitrary segments with dynamically varying voltage, activity are predicted. role nitrogen gate...
Threshold voltage shift (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) due to negativebias temperature instability (NBTI) in p-FinFETs with replacement metal gate-based high-k gate process is measured using an ultrafast method. A comprehensive modeling framework involving uncorrelated contributions from the generation of interface traps xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ), hole trapping preexisting...
A modeling framework is proposed to predict the degradation and recovery of threshold voltage shift (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) due negative bias temperature instability. Double interface reaction- diffusion model with transient trap occupancy used generation traps xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ). Empirical stretched exponential equations are capture hole trapping detrapping in preexisting...
The time kinetics of interface trap generation and passivation (ΔN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ) its contribution (ΔV during after negative bias temperature instability (NBTI) stress is calculated by using Sentaurus TCAD. framework consists process for the formation realistic device structures to obtain material strain information, while used implement double-interface reaction-diffusion (RD) model kinetics....
An ultrafast (10-μs delay) measurement technique is used to characterize the negative bias temperature instability-induced threshold voltage shift (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) in replacement metal gate-based high-K gate Si and SiGe p-FinFETs. The dc stress-recovery ΔV time kinetics, acceleration factor (VAF), activation energy (E xmlns:xlink="http://www.w3.org/1999/xlink">A</sub> are compared for different...
Threshold voltage shift (ΔVT) due to Negative Bias Temperature Instability (NBTI) in p-MOSFETs is modeled using the BTI Analysis Tool (BAT) framework. The ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> time kinetics during and after DC AC stress at different (VGSTR) recovery (VGREC) biases, temperature (T), pulse duty cycle (PDC) frequency (f) modeled. influences of Nitrogen content (N%) gate insulator stack, Germanium (Ge%) channel,...
The Reaction-Diffusion-Drift model is validated as a trap generation framework during Bias Temperature Instability (BTI), Stress Induced Leakage Current (SILC), and Time Dependent Dielectric Breakdown (TDDB) experiments. implemented in standalone Technology CAD (TCAD)-based deterministic stochastic versions. Different implementations show equivalence of the time kinetics stress passivation after stress. trigger for different type experiments introduced via single reaction parameter. against...
As feature sizes of transistors began to approach atomic levels, aging effects have become one major concerns when it comes reliability. Recently, a subject voltage scaling as the latter entered sub-μs regime. Hence, shifted from sole long-term (as treated by state-of-the-art) short and reliability challenge. This paper interrelates both explore quantify for first time short-term aging. We propose "aging-awareness" with respect which is indispensable sustain runtime Otherwise, transient...
The TCAD framework developed in part-I of this paper is used to study the impact fin length (FL) and width (FW) scaling on interface trap generation (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ) during negative bias temperature instability (NBTI) FinFETs. Structure mechanical stress are obtained by Sentaurus process. device having capture-emission depassivation (CED) multistate configuration (MSC) models for kinetics. strain...
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NBTI stress and recovery temporal kinetics at different experimental conditions are predicted in Si SiGe (having cap) p-MOSFETs. Mutually uncorrelated contributions from interface (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ) bulk xmlns:xlink="http://www.w3.org/1999/xlink">OT</sub> trap generation hole trapping xmlns:xlink="http://www.w3.org/1999/xlink">HT</sub> pre-existing traps used to calculate overall threshold voltage...
A framework is proposed for activity-dependent timing degradation due to p-FET negative bias temperature instability (NBTI) in digital circuits. fixed-time compact model NBTI and validated with physical predictions various circuits under different input signal slew fan-out load conditions. The used predict the arbitrary activities. An equivalent level found that can be applied all p-FETs circuit serve as an upper bound of activity avoid conservative worst case dc analysis. dependence studied...
An ultrafast characterization method is used to study DC and AC NBTI in Si SiGe channel core RMG p-FinFETs. The time evolution of degradation during after stress, the impact stress bias, temperature, frequency duty cycle are characterized. A physics-based model qualitatively explain measured data. similarities differences devices highlighted.
Negative Bias Temperature Instability (NBTI) is due to interface trap generation (ΔN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ) and trapping of holes in gate insulator traps xmlns:xlink="http://www.w3.org/1999/xlink">HT</sub> ). However, the isolation methods relative dominance ΔN , time constants for stress, recovery associated temperature (T) activation, whether recovers or remains permanent after are widely debated. The...
The physics-based BTI Analysis Tool (BAT) is used to model the time kinetics of threshold voltage shift (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) during and after NBTI in p-channel planar bulk FDSOI MOSFETs SOI FinFETs. BAT uses uncorrelated contributions from trap generation at channel/gate insulator interface xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> gate xmlns:xlink="http://www.w3.org/1999/xlink">OT</sub> ), hole...
A deterministic reaction-diffusion–drift model is used for the time kinetics of bulk gate insulator trap generation in p-channel Field Effect Transistors (FETs) under inversion stress. The consistency and stochastic versions shown. independently validated using stress-induced leakage current data from various reports. incorporated into already existing bias temperature instability (BTI) analysis tool framework negative BTI data. measured FinFETs having different channel material, substrate...
NBTI in Replacement Metal Gate (RMG) High-K (HKMG) SiGe p-FinFETs is modeled. Time kinetics for DC and AC stress recovery, temperature (T) dependence of voltage acceleration factor (VAF), impact Ge% N% are quantified. Benchmarking done with Si p-FinFETs, process (Ge%, N%) explained by TCAD band structure calculations.
An ultrafast (10-μs delay) measurement technique is used to characterize ac negative-bias temperature instability-induced threshold voltage shift (ΔVT) in replacement metal-gate-based high-K metal gate Si and SiGe p-FinFETs. Time kinetics of stress recovery, acceleration factor, activation energy (EA), frequency (f), pulse duty cycle (PDC) dependence are shown for different germanium percentages (Ge%) the channel nitrogen (N%) insulator. A comprehensive physical model framework based on...
Consistency of the recently proposed deterministic composite modeling framework for Negative Bias Temperature Instability (NBTI) in large area devices is verified stochastic NBTI small devices. The has two independent and uncoupled components, interface trap generation (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ), hole trapping pre-existing defects xmlns:xlink="http://www.w3.org/1999/xlink">HT</sub> ). time evolution mean...
Negative Bias Temperature Instability (NBTI) stress and recovery time kinetics from Replacement Metal Gate (RMG) High-K (HKMG) p-channel FinFETs are measured modeled. The impact of channel length (L) scaling on shift in threshold voltage (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ), its power-law exponent (n), Voltage Acceleration Factor (VAF) (T) activation (E xmlns:xlink="http://www.w3.org/1999/xlink">A</sub> ) is analyzed....
A stochastic reaction-diffusion drift model is used to simulate the time kinetics of interface and bulk oxide traps responsible for bias temperature instability (BTI), stress-induced leakage current (SILC), time-dependent dielectric breakdown (TDDB) in MOSFETs. Trap generation passivation are calculated using dissociation repassivation trap precursors simultaneous diffusion and/or atomic, molecular, ionic species. The average multiple simulations qualitatively explain measured BTI SILC data....
A physical framework is used to model time kinetics of Negative Bias Temperature Instability (NBTI) in Si and SiGe FDSOI p-MOSFETs p-FinFETs. The effects Germanium (Ge%) the channel Nitrogen (N%) High-K Metal Gate (HKMG) gate stack are explained. Mechanical strain terms STI active distance (SA) for length (L) scaling FinFET Band structure calculated correlate process (Ge%, N%, strain) impact on device degradation. included Sentaurus Device TCAD predict NBTI FinFETs.