A5019061501- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Nanowire Synthesis and Applications
- Silicon Carbide Semiconductor Technologies
- Ferroelectric and Negative Capacitance Devices
- Semiconductor Quantum Structures and Devices
- Silicon and Solar Cell Technologies
- 3D IC and TSV technologies
- Semiconductor materials and interfaces
- Radiation Effects in Electronics
- Thin-Film Transistor Technologies
- Copper Interconnects and Reliability
- Advancements in Photolithography Techniques
- Radio Frequency Integrated Circuit Design
- Quantum and electron transport phenomena
- Advanced Surface Polishing Techniques
- Metal and Thin Film Mechanics
- Force Microscopy Techniques and Applications
- Analog and Mixed-Signal Circuit Design
- Advanced Semiconductor Detectors and Materials
- Surface and Thin Film Phenomena
- Electronic and Structural Properties of Oxides
- Silicon Nanostructures and Photoluminescence
- Semiconductor Lasers and Optical Devices
IMEC
2015-2024
KU Leuven
2008-2017
Centro de Investigación de Métodos Computacionales
2014-2015
ON Semiconductor (United States)
2005
STMicroelectronics (France)
2005
Motorola (United States)
2001-2004
Université Jean Monnet
2004
Jet Propulsion Laboratory
2001-2003
UCLouvain
2002
University of California, Davis
1999-2002
This paper presents a new integration scheme to fabricate Si/Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.55</sub> Ge xmlns:xlink="http://www.w3.org/1999/xlink">0.45</sub> heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. 1- μm length on excess of 20 μA/μm at VGS=VDS=1.2 V. Low-temperature measurements, performed suppress trap-assisted (TAT), reveal the point...
This paper presents the low-frequency noise (LFN) behavior of vertical tunnel FETs (TFETs). The experimental input characteristics with different source compositions (Si and Ge) HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> thicknesses in gate-stack (2 3 nm) are presented. A brief analog parameters analysis, including transconductance, output conductance, intrinsic voltage gain under bias conditions, shows that TFETs promising for...
This paper discusses the electrical characterization of complementary multiple-gate tunneling field effect transistors (MuGTFETs), implemented in a MuGFET technology compatible with standard metal oxide semiconductor (CMOS) processing, emphasizing dependence current on fin-width. A linear for narrow fins square root fin width is experimentally reported first time. The comparison between and planar-like offers additional insights about fin-width dependence. output characteristic shows perfect...
This paper presents, for the first time, experimental comparison between p-type trigate FinFET and p-TFET analog performances devices fabricated on same wafer. A careful analysis of electrical characteristics is performed to choose best bias conditions these devices. higher intrinsic voltage gain obtained because their better output conductance, which more than four orders magnitude one p-FinFET transistors at from room temperature up 150 <formula formulatype="inline"...
Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to fabricate these allow them be integrated with FinFET devices. Device and circuit simulations explain the device explore new applications using this device. A novel application of MIGFET as a signal mixer has demonstrated. undoped channel, very thin body, perfectly matched gates allows charge coupling two signals provide family mixer. Since...
This paper presents a new integration scheme for complementary hetero-junction vertical Tunnel FETs (VTFETs), whereby sacrificial source layer is used during the device fabrication and replaced by final hetero-source materials, respectively n- or p-TFETs, thereby minimizing thermal budget applied to junctions. With demonstration of this source-replacement-last module Ge n-TFET, we show that it possible grow highly doped hetero-junctions on Si channel with steep doping profiles without...
Trap-assisted tunneling (TAT) is a major hurdle in achieving sub-60-mV/decade subthreshold swing (SS) tunnel field-effect transistors (TFETs). This paper presents an insight into the TAT process presence of field-induced quantum confinement (FIQC) line TFETs. We show that SS degradation TFETs mainly caused by through traps located bulk semiconductor nearby gate dielectric. For Si n-type TFET, energy quantization conduction band found to suppress interface-region several orders magnitude and...
InGaAs homojunction Tunnel FET devices are demonstrated with sub-60 mV/dec Sub-threshold Swing (SS) measured in DC. A 54 SS is achieved at 100 pA/μm over a drain voltage range of 0.2–0.5 V. The remains 1.5 orders magnitude current room temperature. Trap-Assisted Tunneling (TAT) found to be negligible the device evidenced by low temperature dependence transfer characteristics. Equivalent Oxide Thickness (EOT) play major role achieving performance. EOT 0.8 nm.
We evaluate Power-Performance-Area & Cost (PPAC) for nanosheet (NS), forksheet (FS), monolithic sequential Complementary FET (CFET) at 5 4 track (T) designs with tight gate pitch (CPP) metal (MP). While NS FS prove unsuitable 4T designs, CFETs provide a performant cost-effective solution.
Over the last years there has been lots of interest in use germanium and III-V compounds as potential replacements for silicon channels. Germanium with its high hole mobility attracted attention application advanced pMOS devices. Indium gallium arsenide compounds, their intrinsically superior electron saturation velocity, are considered a candidate nMOS devices beyond 14 nm node technology.
The continued physical feature size scaling of CMOS transistors is experiencing asperities due to several factors (physical, technological, and economical), it expected reach its boundary in the coming years. Sequential-3D (S3D) integration has been perceived as a promising alternative continue benefits offered by semiconductor scaling. This paper addresses different variants S3D potential challenges achieve realizable solution. We analyze quantify observed sequential at die level.
In this paper, we report on FD-SOI with high-k and single metal gate as a possible candidate for the 32 nm LOP LSTP nodes. Good I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> performance nMOS pMOS transistors in ultra-low-leakage regime (I =6.6 pA/μm) are presented. addition co-integration of high voltage devices EOT 29A/V xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> 1.8...
The successful implementation of nanowire (NW) based field-effect transistors (FET) critically depends on quantitative information about the carrier distribution inside such devices. Therefore, we have developed a method high-vacuum scanning spreading resistance microscopy (HV-SSRM) which allows two-dimensional (2D) profiling fully integrated silicon NW-based tunnel-FETs (TFETs) with 2 nm spatial resolution. key elements our characterization procedure are optimized NW cleaving and polishing...
In this paper, we present for the first time a novel Si p-tunnel field effect transistor (pTFET) with high-k dielectric and metal gate fabricated in multiple technology. The device exhibits an on-state current of 7 µA/µm at VDD 0.9 V high ION/IOFF ratio ∼106 fin width 10 nm. on-current is believed to be due enhanced electric caused by silicide encroachment dopant segregation. Low variability performance reported different widths. Temperature measurements also show that transport mechanisms...
The Ge-source tunnel FETs (TFETs) are fabricated using a novel replacement-source approach, whereby dummy source is replaced at the end of process flow by final material to form an heterojunction. We show that can be successfully while maintaining gate dielectric integrity in gate-source overlap (GS-OL) region and selectively exposed materials. Due situ-doped epitaxial-grown low thermal budget, this integration scheme leads formation highly doped abrupt heterojunction allows complementary...
InGaAs planar TFETs with 70% In content are fabricated and characterized. The increase of the 8 nm channel from 53% to is found significantly boost performance device. Record Ion=4 μA/μm at If = 100 μA/μm, Vdd=0.5V Vd=0.3 V minimum sub-threshold swing (SSmm) 60 mV/dec 300K obtained for a homo-junction Reliability assessment shows that TFET SS transconductance (gm) more immune PBTI stress than its equivalent MOSFET
The goal of this paper is to study the analog performance parameters tunnel field-effect transistors (TFETs) with different source compositions and process conditions. experimental matrix included devices either a 100% silicon or Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1–<i>x</i></sub> Ge xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> source, so that germanium amount at source/channel interface could be correlated...
We study the positive bias temperature instability (PBTI) of InGaAs tunnel-FETs (TFETs) with two different indium fractions (53% and 70%) compare reference MOSFETs, using same gate stack. While identical threshold voltage is found irrespective device type, subthreshold swing (SS) TFETs to be more robust against PBTI as compared MOSFETs. With aid comprehensive TCAD simulations, we show that SS a TFET intrinsically less sensitive interface/oxide border traps, thanks narrow energy range swept...
3D stacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at 45nm fin pitch and 110nm poly technology. This demonstrates the compatibility of aggressive device density advanced nodes thanks to tight alignment precision first processed top layer last bottom through silicon channel bonding stack during 193nm immersion lithography. The are junction-less fabricated low temperature (T ≤ 525 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
We show the impact of process parameters on electrical performance complementary Multiple-Gate Tunneling Field Effect Transistors (MuGTFETs), implemented in a MuGFET technology compatible with standard CMOS processing. Firstly, gate oxide thickness and implant doping conditions tunneling is analyzed compared TCAD simulations. Secondly, three different annealing are compared: spike anneal, sub-ms laser anneal low temperature for Solid Phase Epitaxy Regrowth (SPER). Surprisingly, SPER shows...