A5033966941- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Copper Interconnects and Reliability
- Nanowire Synthesis and Applications
- Integrated Circuits and Semiconductor Failure Analysis
- Surface Modification and Superhydrophobicity
- Silicon and Solar Cell Technologies
- Advanced Surface Polishing Techniques
- Ultrasound and Cavitation Phenomena
- Electrohydrodynamics and Fluid Dynamics
- Fluid Dynamics and Heat Transfer
- Advancements in Photolithography Techniques
- Semiconductor materials and interfaces
- Silicon Nanostructures and Photoluminescence
- Fluid Dynamics and Thin Films
- Thin-Film Transistor Technologies
- Microfluidic and Bio-sensing Technologies
- Metal and Thin Film Mechanics
- 3D IC and TSV technologies
- Anodic Oxide Films and Nanostructures
- Industrial Vision Systems and Defect Detection
- Nanomaterials and Printing Technologies
- Electronic and Structural Properties of Oxides
- Aerosol Filtration and Electrostatic Precipitation
- Semiconductor Quantum Structures and Devices
IMEC
2015-2024
SCREEN (Japan)
2018
Lam Research (Austria)
2010-2016
GlobalFoundries (United States)
2015
Centro de Investigación de Métodos Computacionales
2014
KU Leuven
2001-2003
Spectacular progress in developing advanced Si circuits with reduced size, along the track of Moore's law, has been relying on necessary developments wet cleaning nanopatterned wafers to provide contaminant free surfaces. The most efficient is achieved when complete wetting can be realized. In this work, ordered arrays silicon nanopillars a hitherto unexplored small scale have used study behavior nanomodulated surfaces substantial range surface treatments and geometrical parameters. With use...
This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: Q factor increased to 25 as compared our previous work, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> = 500 μA/ μm at xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> 100 nA/μm achieved, approaching best...
Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal nanowire (NW) demonstrated, the process flow described in this paper can be adjusted to make vertically stacked NWs increase drive per footprint. The short-channel have round 9-nm diameter and GAA smallest channel gate dimensions (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
We demonstrate Si-cap-free SiGe p-channel FinFETs and gate-all-around (GAA) FETs in a replacement metal gate (RMG) process, for Ge contents of 25% 45%. show that the performance these devices is substantially improved by high-pressure (HP) deuterium (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) anneal, which ascribed to 2x reduction interface trap density xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ). Furthermore, it found...
Dealing with nanometer-sized particulate contamination is still one of the major challenges during manufacturing yielding semiconductor devices. This especially true for increasing number critical processing steps, where residues matter need to be removed without mechanically damaging sensitive device patterns and, at same time, achieve lowest possible substrate loss. If higher loss would permitted, a more or less pure chemical mechanism could employed (e.g. particle undercut by etching and...
Wet chemical etching is a key process in fabricating silicon (Si) nanostructures. Currently, wet of Si proposed to occur through the reaction surface atoms with etchant molecules, forming etch intermediates that dissolve directly into bulk solution. Here, using situ transmission electron microscopy (TEM), we follow nanoscale dynamics amorphous (a-Si) nanopillars real-time and show generated during alkaline first aggregate as nanoclusters on then detach from before dissolving Molecular...
Silicon germanium (SixGe1–x or SiGe) is an important semiconductor material for the fabrication of nanowire-based gate-all-around transistors in next-generation logic and memory devices. During process, SiGe can be used either as a sacrificial layer to form suspended horizontal Si nanowires or, because its higher carrier mobility, possible channel that replaces both vertical nanowires. In cases, there pressing need understand develop nanoscale etching processes enable controlled selective...
Abstract Recent surge in demand for computational power combined with strict constraints on energy consumption requires persistent increase the density of transistors and memory cells integrated circuits. Metal interconnects their current form struggle to follow size downscaling due materials limitations at nanoscale, causing severe performance losses. Next‐generation need new materials, molybdenum (Mo) is considered best choice, offering low resistivity, good scalability, barrierless...
In situ characterization of the underwater stability superhydrophobic micro- and nanostructured surfaces is important for development self-cleaning antifouling materials. this work, we demonstrate a novel attenuated total reflectance-Fourier transform infrared (ATR-FTIR) spectroscopy-based method large-area wetting silicon nanopillars. When air present in between structures, as characteristic Cassie-Baxter state, relative intensities water bands absorption spectrum change because...
Cleaning of nanoparticles (< 50nm ) is becoming a major challenge in semiconductor manufacturing and the future use traditional methods, such as megasonic cleaning, questioned. In this paper capability cleaning to remove without inflicting damage fragile structures investigated. The role dissolved gas efficiency indicates that cavitation main mechanism. Consequently mass-balance analyses are needed optimize performance tools. When present tools can down about 30 nm using dilute...
An approach for wet-chemical atomic layer etching (WALE) of semiconductors is described. The surface chemistry InAs was investigated HCl/H2O2 solutions suitable controlled in the low etch rate range (<0.1–10 nm min−1). Kinetic studies were performed using inductively coupled plasma – mass spectrometry (ICP-MS). As GaAs and InGaAs, importance Cl− ion kinetics demonstrated a chemical reaction scheme presented to help understand chemistry. A detailed study an alternative two-step process...
Superhydrophobic surfaces are highly promising for self-cleaning, anti-fouling and anti-corrosion applications. However, accurate assessment of the lifetime sustainability super-hydrophobic materials is hindered by lack large area characterization superhydrophobic breakdown. In this work, attenuated total reflectance-Fourier transform infrared spectroscopy (ATR-FTIR) explored a dynamic study wetting transitions on immersed arrays silicon nanopillars. Spontaneous breakdown state triggered...
This paper addresses the opportunities and challenges of wet dry selective etches in integration gate-all-around (GAA) field-effect transistor (FET), which is emerging as a promising solution to replace FinFET for advanced logic devices. For GAA device fabrication, quintessential challenge controlled isotropic etching dielectrics, semiconductors, metals with high selectivity exposed materials. In this paper, significance unit process modules integration: shallow trench isolation (STI), inner...
Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, first time, integration of tungsten (W) BPR lines with Si finFETs. technology requires insertion metal in front-end-of-line (FEOL) stack. poses risks stack deformation and device degradation due to metal-induced stress contamination. To assess deformation, we demonstrate W-BPR which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting...
Interconnect options will be introduced and reviewed targeting tight pitch metal layers at the local levels. Examples include hybrid metallization, semi-damascene interconnects as well potential new conductor materials.
The Gate All-Around device architecture requires the formation of semiconductor nanowires. As an example SiGe nanowires can be formed by selective removal rSi in a Si-SiGe fin-shaped stack. In this paper we will show how alkaline solutions used for Si to and Ge. We also that anisotropy etch is not extension Si, even at low moderate Ge concentrations (Ge ≤ 50%).
Robust processes to fabricate densely packed high-aspect-ratio (HAR) vertical semiconductor nanostructures are important for applications in microelectronics, energy storage and conversion. One of the main challenges manufacturing these is pattern collapse, which damage induced by capillary forces from numerous solution-based used during their fabrication. Here, using an array silicon (Si) nanopillars as test structures, we demonstrate that collapse can be greatly reduced a solution-phase...
Abstract With the persistent downscaling of integrated circuits, molybdenum (Mo) is currently considered a potential replacement for copper (Cu) as material metal interconnects. However, fabricating nanostructures with critical dimensions order 10 nm and below challenging. This because very high density grain boundaries (GBs) results in highly non‐uniform surface profiles during direct wet etching. Moreover, etching Mo conventional aqueous solutions problematic, products oxidation have...
Abstract Molybdenum (Mo) has emerged as a promising material for advanced semiconductor devices, especially in the design and fabrication of interconnects requiring sub‐10 nm metal nanostructures. However, current wet etching methods Mo using aqueous solutions struggle to achieve smooth profiles at such scales. To address this problem, we explore chemical patterned nanowires (NWs) an organic solution: ceric ammonium nitrate (CAN) dissolved acetonitrile (ACN). In study, demonstrate two...
Dense arrays of high-aspect-ratio (HAR) vertical nanostructures are essential elements microelectronic components, photovoltaics, nanoelectromechanical, and energy storage devices. One the critical challenges in manufacturing HAR is to prevent their capillary-induced aggregation during solution-based nanofabrication processes. Despite importance controlling capillary effects, detailed mechanisms how a solution interacts with not well understood. Using situ liquid cell transmission electron...
Anisotropic wet etching of crystalline silicon (c-Si) is a key chemical process used in microelectronic device fabrication. Controlled fabrication c-Si nanostructures requires an understanding how crystal planes evolve during etching. Here, by imaging KOH nanowires, we show that it possible to switch the fast-etching direction (i.e., etch anisotropy) between Si {100} and {110} at will through mechanical agitation etchant. Based on molecular dynamics simulations, attribute this switching...