A5008296538- Copper Interconnects and Reliability
- Semiconductor materials and devices
- Electronic Packaging and Soldering Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Semiconductor materials and interfaces
- Advancements in Semiconductor Devices and Circuit Design
- 3D IC and TSV technologies
- Metal and Thin Film Mechanics
- Advancements in Photolithography Techniques
- Low-power high-performance VLSI design
- VLSI and Analog Circuit Testing
- Advanced Surface Polishing Techniques
- Graphene research and applications
- Electrodeposition and Electroless Coatings
- Ferroelectric and Negative Capacitance Devices
- Silicon Carbide Semiconductor Technologies
- Optical Coatings and Gratings
- Electromagnetic Compatibility and Noise Suppression
- Electron and X-Ray Spectroscopy Techniques
- Advanced ceramic materials synthesis
- Advanced Data Storage Technologies
- Electrostatic Discharge in Electronics
- Mesoporous Materials and Catalysis
- Nanofabrication and Lithography Techniques
- Electrical Contact Performance and Analysis
IMEC
2016-2025
Imec the Netherlands
2010-2025
University of California, San Diego
2021
University of San Diego
2021
KU Leuven
2002-2015
Bellingham Technical College
2015
University of Pisa
2000
Atomic layer deposition of ruthenium is studied as a barrierless metallization solution for future sub-10 nm interconnect technology nodes. We demonstrate the void-free filling in wide single damascene lines using an ALD process combination with 2.5 Å TiN interface and postdeposition annealing. At such small dimensions, effective resistance depends less on scaling than that Cu/barrier systems. Ruthenium potentially crosses Cu curve at 14 10 according to semiempirical model advanced These...
We investigate the impact of wire geometry on resistance, capacitance, and RC delay Cu/low-k damascene interconnects for fixed line-to-line pitch. The resistance is computed by applying a semiempirical resistivity model, calibrated to Cu wires, integrated with Ru-based liner, currently investigated 7 nm logic technology node. capacitance simulated means 2D field solver (Raphael) Synopsys. line dimensions analyzed case 32 pitch interconnects, which are representative show that aspect ratios...
Reliability challenges of candidate metal systems to replace traditional Cu wiring in future interconnects are discussed. From a reliability perspective, key opportunity is electromigration improvement: due their high melting point and slower self-diffusion kinetics, higher current carrying capabilities possible. Also, the cohesive energy better resistance oxidation some metals potentially allows for barrierless integration, although adhesion properties must be carefully optimized. Besides...
We investigated plasma treatment induced water absorption in a SiOCH low-k dielectric and the influence of absorbed components on reliability. By using thermal desorption spectroscopy (TDS), was evidenced for N2/H2 treatments. Based these TDS results, two anneal temperatures were selected to separate quantify respective contributions components, physisorbed (α) chemisorbed (β) water, With desorbed by an at 190 °C, shows reduced leakage currents slightly improved time-dependent breakdown...
We investigate the dependence of Cu via resistance on dimensions, shape, misalignment, and Co prefill level by means a novel resistivity model, calibrated to actual wires silicon integrated into Synopsys Raphael tool. For this paper, we consider case 16 12nm self-aligned vias, which are representative for 7 5nm logic technology nodes, respectively. Process emulations performed using Sentaurus Explorer tool in order generate 3-D models investigated structures. Finally, is extracted through...
We address RC scaling trends and predict the performance benefits of advanced metallization options with respect to conventional Cu/low-k interconnects. The range interconnect dimensions we cover spans from 22 nm 3 logic technology node. show that Ru Co fills can significantly reduce resistance at narrow pitches. At 12 half-pitch, line via be lowered by up 36% 75%, respectively, replacing Cu barrierless fill; using hybrid via-prefill, half-pitch 42% in 87° tapered vias 52% chamfered vias. As...
Through physical and electrical analysis, the impact of thermal gradients on mass transport in Cu interconnects is studied using a dedicated test structure. The key parameter for thermomigration (TM), heat (Q∗), evaluated experimentally to be 0.21 eV. Furthermore, an analytical model based existing 1D physics-based models [M. A. Korhonen et al., J. Appl. Phys. 73, 3790–3799 (1993); H. Zahedmanesh Microelectron. Reliab. 111, 113769 (2020)] proposed predict time void nucleation, growth rate...
Periodic mesoporous organosilicas (PMOs) are one of the most promising candidates to be used as ultra-low-k dielectrics in microelectronic devices. In this paper, PMO thin films that combine an value, a hydrophobic property and high resistance against aggressive chemical conditions presented. The synthesized via spin-coating 1,1,3,3,5,5-hexaethoxy-1,3,5-trisilacyclohexane, hydrochloric acid, water ethanol mixture using polyoxyethylene (10) stearyl ether porogen template. obtained highly...
The alternative metals Ru and Co are benchmarked to Cu in a damascene vehicle at scaled dimensions. nanowires have higher resistivity but show, when barrierless, lower increase of the line resistance versus trench cross-sectional area compared Cu. Therefore, both superior for trenches smaller than 250nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . electrical benchmark is complemented with via predictions using calibrated models....
High-aspect-ratio (HAR) Ru power rails, buried in front-end-of-line (FEOL) oxide, can potentially replace conventional middle-end-of-line (MOL) Cu rails. The HAR feature boost performance by reducing resistance and voltage drop along the line. nature, helps to minimize standard cell height freeing up routing resources at MOL, enabling overall area scaling. This paper demonstrates, lines of aspect ratio 7, a CD 18 nm. Line these dimensions, measures 60 Ω/µm, with minimum electrical...
Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, parasitics between vertical (VFETs) gate-all-around (GAA) transistors with (LFETs) targeting 5nm. We reviewed some of unique considerations VFET circuit influences.
This paper presents a vertical gate-all-around nanowire FET (VFET) architecture targeting 5nm and beyond technologies, new standard-cell construct for digital flow implementation. VFET technology circuits parasitics processes design features aligned with CMOS are systematically assessed the first time. Self-aligned quadruple pattering (SAQP) is implemented to achieve required 12nm half-pitch interconnects, worst case RC delay corner 1.4X slower than best corner. Our work shows that...
This paper evaluates the impact of backside power delivery on physical implementation a commercial 64-bit high-performance block from ARM™ at A14 node. A BEOL, including TSV connections, is proposed and calibrated using TCAD experimental data. The developed stack modeled in cell-level parasitic extraction tool to enable its use during place route. same benchmark physically implemented imec's own PDK. PDN enables frequency improvements 2% 6% compared frontside PDN, stemming core area...
Continued scaling dimensions of interconnects used for Si chip integration reduces the available cross sectional area conduction. As Cu requires a protective diffusion barrier, TaN and liner such as Co or Ru is frequently chosen to fulfill various requirements time dependent dielectric breakdown (TDDB). Due higher resistivity, barrier/ thickness with line dimension desirable, but has proven difficult much below 2nm. One aspect here limited conformality when using physical vapor deposition...
Interconnect options will be introduced and reviewed targeting tight pitch metal layers at the local levels. Examples include hybrid metallization, semi-damascene interconnects as well potential new conductor materials.
The effect of porosity on the electrical properties porogen-free ultralow-k dielectric materials was demonstrated using a special curing process that allows separate control and matrix properties. It is shown leakage current insensitive to porosity, suggesting bulk conduction mechanism. On other hand, higher leads lower breakdown voltage, indicating can degrade reliability performance material. observed field explained in terms amount cage structure film, exacerbation strain Si–O–Si backbone...
Back end of line (BEOL) reliability strongly depends on the absolute temperature and distribution in interconnect lines. In this work, we present a holistic approach that combines experimental characterization, such as BEOL self-heating measurements material properties with hybrid modeling to investigate impact design, materials, technology options BEOL. The thermal coupling from Front End Line (FEOL) is also investigated work.
A new strategy to seal mesoporous low-k thin films with a pore size of 3 nm has been developed. This is achieved by spin-coating self-assembled carbon-bridged organosilica layer followed grafting hexamethyl disilazane.
We discuss the selection and assessment of alternative metals by a combination ab initio computation electronic properties, experimental resistivity assessments, calibrated line resistance models. Pt-group as well Nb are identified most promising elements, with Ru showing best material properties process maturity. An Ru, Ir, Co lines down to ~30 nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is then used devise compact models for via...
Interconnects pose increasing challenges as technology scaling proceeds. In order to overcome these simultaneous optimization of novel metallization schemes, new materials, circuit and system level approaches are required.
This paper summarizes findings on the iN7 platform (foundry N5 equivalent) for single exposure EUV (SE EUV) of M1 and M2 BEOL layers. Logic structures within these layers have been measured after litho etch, variability was characterized both with conventional CD-SEM measurements as well Hitachi contouring method. After analyzing patterning layers, impact potential interconnect reliability studied by using MonteCarlo process emulation simulations to determine if current litho/etch...
The integration of a three-layer BEOL process which includes an intermediate 21 nm pitch level, relevant for the 3 technology node, is demonstrated. A full barrier-less Ruthenium (Ru) dual-damascene (DD) metallization allowed to test different dimensions minimum island, via extension and tip-to-tip (T2T). Five-track place route (PNR) SRAM constructions were realized with self-aligned block (SAB) technique. Stacked vias showed resistance modulation size island due change in chamfer. High...
The electrical conduction of a SiCOH based ultralow-k (k = 2.0) dielectric is investigated over an electric field range from 1.0 MV/cm to breakdown. Below 4.0 MV/cm, space-charge-limited current dominates the leakage. Above 5.0 transition found trap-assisted Fowler-Nordheim (F-N) tunneling F-N tunneling. It hypothesized that under stress, intrinsic material degradation causes positively charged defects generated in dielectric. Moreover, this change dominant path has significant impact on...