A5082055359- Semiconductor materials and devices
- Copper Interconnects and Reliability
- Advancements in Semiconductor Devices and Circuit Design
- 3D IC and TSV technologies
- Silicon Carbide Semiconductor Technologies
- Electromagnetic Compatibility and Noise Suppression
- Integrated Circuits and Semiconductor Failure Analysis
- Microwave Engineering and Waveguides
- Electronic Packaging and Soldering Technologies
- Advancements in Photolithography Techniques
- Semiconductor materials and interfaces
- Energy Harvesting in Wireless Networks
- Microwave and Dielectric Measurement Techniques
- Electrical Contact Performance and Analysis
- Ferroelectric and Negative Capacitance Devices
- Semiconductor Lasers and Optical Devices
- Low-power high-performance VLSI design
- Electrostatic Discharge in Electronics
- Quantum and electron transport phenomena
IMEC
2015-2024
National Institute of Astrophysics, Optics and Electronics
2009-2014
The integration of a three-layer BEOL process which includes an intermediate 21 nm pitch level, relevant for the 3 technology node, is demonstrated. A full barrier-less Ruthenium (Ru) dual-damascene (DD) metallization allowed to test different dimensions minimum island, via extension and tip-to-tip (T2T). Five-track place route (PNR) SRAM constructions were realized with self-aligned block (SAB) technique. Stacked vias showed resistance modulation size island due change in chamfer. High...
An experimental method for separately determining the contribution of conductor and dielectric losses to signal attenuation occurring in PCB transmission lines is presented this paper. This based on an analytical extraction model parameters propagation constant takes into consideration dominant effects influencing attenuation. It demonstrated through a careful model-experiment correlation that application allows accurate representation loss mechanisms technology. Furthermore, frequency...
A method to evaluate hot-carrier-induced degradation in MOSFETs and incorporating the corresponding effect into RF small-signal model is presented. The based on controlled gradual of a common-source configured RF-MOSFET by applying high drain-to-source dc voltage. For this purpose, electrical stress monitored through current measured at bulk terminal separated from pads used collect S-parameters, which allows precise definition condition. parameters are determined S-parameters for fresh...
3D stacked devices without area penalty from device-device space, such as complementary FET (CFET), is promising for post-nanosheet CMOS scaling. New MOL architectures, backside power delivery network (BSPDN) or Vertical-Horizontal-Vertical routing style, are required to connect wiring congestions and resistance increase. Process/material innovations necessary enable high aspect ratio integration in CFET with new architectures.
In this work, we present an efficient methodology for designing and evaluating the performance of current future multi-Gb/s chip-to-chip interconnects Systems on Package (SoP). We analyze coupling between neighboring stripline microstrip lines in single ended differential configurations. Furthermore, method also considers conductor dielectric losses. order to obtain system bandwidth area efficiency, exhaustive analysis downscaled versions SoP was carried out. This allowed find optimal...
We report the implementation of a negative resistance (NR) device with single MOSFET. This effect is achieved by biasing regular 28-nm n-type Metal-Oxide Field-Effect Transistor (nMOSFET) as Bipolar Junction (BJT) gate left floating. The NR has controllable peak-to-valley current ratio (PVCR) that goes from about 1.7 up to value 5.5 when varying temperature 375 K down 80 K. Experimental results at room were compared numerical simulations confirm combined action superficial MOS-like-driven...
This study presents an innovative approach to characterize the reliability of back-end-of-line (BEOL) dielectrics, particularly focusing on breakdown between metal tips. By using a design-representative test structure, we implement novel experimental procedure, referred as "double V -ramp stress", discriminate various failure modes, including line-to-line (L2L), via-to-line (V2L) and tip-to-tip (T2T) breakdowns, distinctly investigate them. The procedure involves 4-point voltage stress...
An analysis of the level hot carrier (HC) degradation caused in sub-100 nm n-type MOSFETs operated from DC up to 20 GHz, is introduced. The comes accompanied with experimental results. process done through application controlled currents at well defines periods time. recorded S-parameters before and after allows observation corresponding changes transmission reflection features, as intrinsic channel resistance transconductance. This relevant for power CMOS amplifiers operating RF frequency regime.
Abstract We investigated the impact of current spreading on resistance short-range connections by performing simulations in Synopsys Sentaurus, based a calibrated resistivity model. As main case study, we considered vertical-horizontal-vertical (VHV) connections, novel cell-routing architecture two-level middle-of-line scheme, that has been proposed to boost routing four-track standard cells beyond 2 nm technology node. analyzed vias and line geometry VHV link found low aspect ratio (AR)...
A new cell routing architecture called vertical-horizontal-vertical (VHV) which requires a two-level (2L) middle-of-line (MOL) scheme has been proposed as scaling booster to enable 4-track (4T) standard (SDC) templates for beyond the 2 nm technology node. In this work, we demonstrate an innovative integration strategy using semi-damascene technique implement 4T VHV, enabling precise definition of tight boundary between SDC's two vias with zero-line extension facing each other and tip-to-tip...
The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 pitch layer, is demonstrated. Place-and-route (PnR) simulations the Power Delivery Network (PDN) proved IR-drop reduction with respect to stacked-via configuration. SV first and last approaches were electrically tested using full barrierless ruthenium (Ru) on dielectric low-k 3.0. A maximum AR = 3.8 was achieved ~2.4 times lower resistance than alternative Thermal shock tests...
The integration of high aspect-ratio (AR) vias or supervias (SV) with a min CD <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bottom</inf> = 10.5 nm and max AR 5.8 is demonstrated, allowing comparison between ruthenium (Ru) cobalt (Co) chemical vapor deposition (CVD) metallizations. Ru gave resistance ~2x higher than Co when 1.1 titanium nitride (TiN) film, realized by atomic layer (ALD), was used as an adhesion/nucleation layer. lowest SV 56 Ω...
High aspect-ratio (AR) 3-level Supervias (SV), with a minimum bottom CD of 15.5 nm and AR = 7.7 are successfully integrated in 3nm node chip. SV directly connects M <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> xmlns:xlink="http://www.w3.org/1999/xlink">x+3</inf> metal layers, without connecting to the intermediate two layers. Enabling such high is achieved by fine tuning etch process guarantee uniform landing straight vertical...
To overcome the micro loading effect that happens during M2 trench etch, an Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> etch stop layer is successfully implemented in our test vehicle with minimum 21nm metal pitch dual-damascene interconnects. Two integration challenges are investigated: via opening difficulty 2nm and undercut issue 5nm layer. Potential solutions proposed...
High aspect-ratio (AR) 3-level Supervias (SV), with a minimum bottom CD of 12.1 nm, AR = 9.4 and > 93 % electrically active SV are successfully integrated in Back-End Line (BEOL) test vehicle Metal Pitch 36. directly connects M <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> xmlns:xlink="http://www.w3.org/1999/xlink">X+3</inf> metal layers, without connecting to the intermediate two layers is potential scaling booster for future...
Complementary FET (CFET) is a device architecture where n-and p-MOS transistors are stacked. As result, the source and drain contact metals also need to be In this work, we tackle high aspect-ratio (AR) patterning metallization required for monolithic CFET integration scheme. The bottom formed by filling trenches with W up AR =16 CD =12 nm, followed CMP metal etch back at 45, 50 60 nm pitch printed EUV lithography. We study accuracy of EB process using scatterometry, TEM new CDSEM technique,...
For the past 50 years, Moore’s law has been well followed by semiconductor industry. The scaling of transistors and interconnects enabled not only various technological advancements but also novel patterning approaches. However, in order to keep up with law, further shrinking at all levels integrated circuit is needed. Among them back end line (BEOL), where increasingly smaller metal pitches require tight specifications for vias connecting lines. In this paper, BEOL via shrink options...