A5060068281- Advancements in Photolithography Techniques
- Electron and X-Ray Spectroscopy Techniques
- Integrated Circuits and Semiconductor Failure Analysis
- Semiconductor materials and devices
- Industrial Vision Systems and Defect Detection
- Silicon and Solar Cell Technologies
- Block Copolymer Self-Assembly
- Advanced Surface Polishing Techniques
- Advanced X-ray Imaging Techniques
- Ultrasonics and Acoustic Wave Propagation
- Thermography and Photoacoustic Techniques
- Additive Manufacturing and 3D Printing Technologies
- Non-Destructive Testing Techniques
- Fusion materials and technologies
- 3D IC and TSV technologies
- Scientific Measurement and Uncertainty Evaluation
- Optical Coatings and Gratings
- Manufacturing Process and Optimization
- Nanofabrication and Lithography Techniques
- Sensor Technology and Measurement Systems
- Model Reduction and Neural Networks
- Image Processing Techniques and Applications
IMEC
2017-2024
Continuous scaling by extreme ultraviolet (EUV) lithography is tightening the patterning requirements for photoresist materials. Specifically, chemically amplified resists (CAR) are facing significant challenges to keep supporting needs. In view of this, complementing EUV with directed self-assembly (DSA) block copolymers offers interesting opportunities enable use CAR towards ultimate resolution. As DSA decouples resist performance from final pattern quality, roughness and defects in can be...
For many years traditional 193i lithography has been extended to the next technology node by means of multi-patterning techniques. However recently such a became challenging and expensive push beyond for complex features that can be tackled in simpler manner Extreme UltraViolet Lithography (EUVL) technology. Nowadays, EUVL is part high-volume manufacturing device landscape it reached critical decision point where one further single print on 0.33NA full field scanner or move EUV double...
One of the many constrains High Numerical Aperture Extreme Ultraviolet Lithography (High NA EUVL) is related to resist thickness. In fact, one consequences moving from current 0.33NA 0.55NA (high NA) Depth Focus (DOF) reduction. addition, as feature lines shrink down 8nm half pitch, it essential limit aspect ratio avoid pattern collapse. The direct consequence such a situation that thickness 30nm, usually used for 32nm pitch dense line/space (LS), will not be suitable 16nm where target...
Owing to photon shot noise and inhomogeneous distribution of the molecular components in a chemically amplified resist, resist patterns defined by extreme ultraviolet (EUV) lithography tend suffer from stochastic variations. These variations are becoming more severe as critical dimensions continue scale down, can thus be expected major challenge for future use single exposure EUV lithography. Complementing with directed self-assembly (DSA) block-copolymers provides an interesting opportunity...
Imec is currently driving the extreme ultraviolet (EUV) photo material development within imec and equipment supplier hub. EUV baseline processes using ASML NXE3300 full field scanner have been setup for critical layers of N7 (iN7) BEOL process modules with a resist sensitivity 35mJ/cm<sup>2</sup>, 40mJ/cm<sup>2</sup> 60mJ/cm<sup>2</sup> metal, block vias layer, respectively. A feasibility study on higher resists HVM has recently conducted looking at 16nm dense line-space targeted exposure...
Extreme Ultraviolet lithography with a numerical aperture of 0.55 will bring an improved optical contrast for contact hole layers and via layers. This should lead to reduction in the number stochastic defects these To quantify this reduction, adequate inspection methodology is required that can detect, addition standard missing merging defects, holes are only partially opened. In work we demonstrate technique uses backscattered electrons detect defects. first phase beam-settings top-down...
Si/SiGe heterostructures are gaining traction as a starting template in applications such Gate-All-Around Field-Effect Transistor (GAAFET), complementary FET (CFET), and 3-dimensional dynamic random access memory (3D-DRAM), where the SiGe alloy plays role of sacrificial material for channel release. However, formation crystalline defects (e.g. crosshatch) epitaxially grown layers critical part determining overall device performance. As such, it is key to be able control defectivity level...
OPC (optical proximity correction) is a well-known and widely used RET (resolution enhancement technique) in optical lithography, which main purpose improving pattern fidelity process window. relies on CD-SEM (critical dimension scanning electron microscope) images as source of information for EPE (edge placement error) measurement, input the modeling flow. However, pitch scales, stricter specifications, reduced metrology error budget, increasing complexities, create challenges traditional...
Complimentary lithography is already being used for advanced logic patterns. The tight pitches 1D Metal layers are expected to be created using spacer based multiple patterning ArF-i exposures and the more complex cut/block patterns made EUV exposures. At same time, control requirements of CDU, pattern shift pitch-walk approaching sub-nanometer levels meet edge placement error (EPE) requirements. Local variability, such as Line Edge Roughness (LER), Placement Error (LPE), dominant factors in...
As the development of Extreme Ultraviolet Lithography (EUVL) is progressing toward sub-10nm generation, process window becomes very tight. In this situation, local Critical Dimension (CD) variability including stochastic defect directly affects yield loss, and it important to inspect/measure all patterning area interest on chip for verification. paper, by combining Area Inspection SEM (AI-SEM) with large Field Of View (FOV) Die-to-Database-base (D2DB) technologies, we show a comprehensive...
Wafer bonding is a key technology for many advanced chip technologies. For 3D integration, stacking schemes and high-density packaging put stringent requirement on the reliability. Bonding quality can be characterized by absence of voids at interface, as delimit complexity subsequent processing integration steps. Therefore, in-line non-destructive inspection techniques void detection are crucial early-stage full process integration. In this work, we perform comprehensive study We fabricate...
Vote-taking lithography is a method for mitigating mask defects, which has been applied in the 1980's to enhance yield. sums up N different images with identical content, each at 1/N dose, mitigate defects on individual mask. The fundamental assumption that do not correlate position from mask, and so defect will be blended good other N-1 masks. recently brought under attention again consideration EUV lithography, where it might provide temporary solution situations defectivity conditions are...
The semiconductor scaling roadmap shows the continuous node to push Moore's law down next generations. In that context, foundry N5 requires 32nm metal pitch interconnects for advanced logic Back- End of Line (BEoL). 193immersion usage now self-aligned and/or multiple patterning technique combinations enable such critical dimension. On other hand, EUV insertion investigation is still a challenge but, related process flow complexity, presents some clear motivations. Imec has already evaluated...
BackgroundFocus-exposure process window measurement and analysis is an essential function in lithography, but the current geometric approach suffers from several significant deficiencies.AimBy clearly identifying problems with approach, a method will be proposed to address these problems.ApproachThe probabilistic (PPW) here takes metrology uncertainty into account rigorously calculates expected fraction of in-spec features based on settings for best dose/focus presumed random errors dose...
For printing the most critical features in semiconductor devices, single exposure extreme ultraviolet (EUV) lithography is quickly advancing as a replacement for ArF immersion-based multipatterning approaches. However, transition from 193 nm to 13.5 light severely limiting number of photons produced by given source power, leading photon shot noise EUV patterns. In addition, inhomogeneous distribution components inside conventional photoresists adding variability, especially when dimensions...
In this paper we will present initial results for logic and memory features imaged with the TWINSCAN EXE:5000 at ASML-imec high NA lab after successful etch pattern transfer. For applications random metal designs (consisting of tight pitches aggressive tip-to-tips) corresponding via structures have been characterized A14 A10 nodes. As well, bidirectional enabled by be described. applications, from BLP/SNLP layer D1d D0a nodes presented.
As High Numerical Aperture Extreme Ultraviolet Lithography (High NA EUVL) gets ready to step in the integrated circuit manufacturing (ICM) world, more and work is being devoted ensuring that all elements involved process, from materials equipment, will be meet required specifications when time comes. One of most critical pieces such an ecosystem photoresist (PR), material used accurately transfer design wafer. In last years we have observed introduction various effective alternative...
Background: Focus-exposure process window measurement and analysis is an essential function in lithography, but the current geometric approach suffers from several significant deficiencies. Aim: By clearly identifying problems with Geometric Process Window approach, a new method will be proposed to address these problems. Approach: The Probabilistic here takes metrology uncertainty into account rigorously calculates expected fraction of in-spec features based on settings for best dose/focus...
Vote-taking lithography is a method for mitigating mask defects, which has been applied in the 1980s to enhance yield. sums up N different images with identical content, each at 1 / dose, mitigate defects on individual mask. The fundamental assumption that do not correlate position from mask, and so defect will be blended good other − masks. recently reconsidered extreme ultraviolet (EUV) lithography, where it might provide temporary solution situations defectivity conditions are yet meeting...
With continuous scaling and increased design process complexity, there is an increasing need for semiconductor manufacturing control. This calls not only advanced methods more capable tools, but also additional intra-wafer across-lot sampling in order to capture variations and/or changes signatures. In this paper we will demonstrate high speed full wafer metrology use cases from the KLA CIRCL™ platform. The CIRCL platform typically used very throughput inline macro defect inspection. Here...
Inpria has pioneered the development of high-resolution metal oxide (MOx) photoresists designed to unlock full potential EUV lithography. In addition resolution, LWR, and sensitivity enable advanced process nodes, there are also stringent defectivity requirements that must be realized for any resist system. We will review advances in post-etch based on: design formulation, track design, developer etch optimization. present data supporting each these topics quantifying defect impact describe...
Spacer-assisted pitch multiplication is a patterning technique that used on many different critical layers for memory and logic devices. Pitch walk can occur when the spacer process, combination of lithography, deposition etch processes, produce repeating, non-uniform grating space / line CDs. It has been shown spacer-assisted double (SADP), where lithography doubled, be reduced by controlling exposure dose such uniformity final SADP spaces defined core resist mandrel (S1) balanced with...
The key challenge to enable a good defectivity control for extreme ultraviolet (EUV) single expose at 32nm pitch is understand what are the main drivers defect generation. CD one of contributors, and has many sources variability (reticle, imaging, die layout, scanner). paper will first discuss quantification sensitivity CD, identification variations (EUV flare, black border, etch, APC, mask bias etc...). All those effects do not have same consequences on level (only nanobridges be considered...