A5008119792- Semiconductor materials and devices
- 3D IC and TSV technologies
- Advancements in Semiconductor Devices and Circuit Design
- Advancements in Photolithography Techniques
- Integrated Circuits and Semiconductor Failure Analysis
- Low-power high-performance VLSI design
- Nanofabrication and Lithography Techniques
- Copper Interconnects and Reliability
- Electromagnetic Compatibility and Noise Suppression
- VLSI and Analog Circuit Testing
- Electronic Packaging and Soldering Technologies
- Sensor Technology and Measurement Systems
- Advanced Wireless Communication Techniques
- Numerical Methods and Algorithms
- VLSI and FPGA Design Techniques
- Semiconductor materials and interfaces
- Advanced Adaptive Filtering Techniques
- Advanced Data Storage Technologies
Qualcomm (United States)
2019-2021
IMEC
2013-2019
Imec the Netherlands
2014
Sri Venkateswara University
2009
High-aspect-ratio (HAR) Ru power rails, buried in front-end-of-line (FEOL) oxide, can potentially replace conventional middle-end-of-line (MOL) Cu rails. The HAR feature boost performance by reducing resistance and voltage drop along the line. nature, helps to minimize standard cell height freeing up routing resources at MOL, enabling overall area scaling. This paper demonstrates, lines of aspect ratio 7, a CD 18 nm. Line these dimensions, measures 60 Ω/µm, with minimum electrical...
To ensure continuity in technology scaling, system level boosters will need to be introduced complement Design-Technology Co-Optimization. We illustrate this evolution with the introduction of buried power rails and backside delivery. These can provide 20% 30% area scaling benefit respectively. Backside delivery further improves IR drop providing up 15% performance enhancement enabling PPAC at level.
In this article, a power delivery network (PDN) modeling framework for backside-PDN configurations is presented. A configuration contains dense microthrough silicon vias (μTSVs) and power/ground metal stack on the backside of die. This approach separates PDN from conventional signaling back-end-of-the-line (BEOL) improves integrity core utilization. We benchmark technology with front-side BEOL configurations. Owing to lower resistivity compared Cu lines advanced nodes, we use ruthenium...
At 7nm and beyond, designers need to support scaling by identifying the most optimal patterning schemes for their designs. Moreover, can actively help exploring options that do not necessarily require aggressive pitch scaling. In this paper we will illustrate how MOL scheme be optimized achieve a dense SRAM cell; optimizing device performance lead smaller standard cells; metal interconnect stack needs adjusted unidirectional metals vertical transistor shift design paradigms. This...
While waiting for EUV lithography to become ready adoption, we need create designs compatible with both single exposures as well 193i multiple splits strategy technology nodes 7nm and below needed keep the scaling trend intact. However, standard approach of designing cells in two-dimensional directions is no more valid owing insufficient resolution 193-i scanner. Therefore, propose a cell design methodology, which exploits purely one-dimensional interconnect.
This letter proposes for the first time buried powered static random-access memory (SRAM) to achieve enhanced write margin and performance in advanced CMOS technology nodes. The power rail (BPR) SRAM is silicon verified. BPR helps lower bitline wordline resistance by relaxing metal width circuits thereby enhances performance. proposed provides up 340 mV 30.6% improvement read speed, respectively, as compared its conventional counterpart without incurring any area penalty a hardware...
Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography as well device that are considered N10 scaling by exploring their impact on representative designs such standard cells, SRAM and analog contexts. This paper illustrates design angle needs be early in development of node. assessment decisions start from constraints power/performance, area cost, all which create Co-Optimization space.
This work addresses the difficulties in creating a manufacturable M2 layer based on an SADP process for N10/N7 and proposes couple of solutions. For N10 design, we opted line staggering approach which each line-end ends contact. We highlight challenges to obtain reasonable window, both simulation as exposures wafer. The main come from very complex keep mask, consisting complicated 2D structures are challenging 193i litho. Therefore, propose solution perform traditional LELE top mandrel...
Standard-cell design and characterization are presented for 7-nm CMOS platform technology targeting low-power high-performance applications with the tightest contacted poly pitch of 42 nm a metallization 32 in FinFET technology. Two standard-cell architectures 7 nm, 9-track library 7.5-track have been designed, introducing an extra middle-of-line layer to enable efficient layout cells. The cells on average smaller than With strict constraints imposed by self-aligned quadruple patterning...
In this paper, standard cell design for iN7 CMOS platform technology targeting the tightest contacted poly pitch (CPP) of 42 nm and a metal 32 in FinFET is presented. Three architectures iN7, 7.5-Track library, 6.5-Track 6-Track library have been designed. Scaling boosters are introduced libraries progressively: first an extra MOL layer to enable efficient layout three starting with library; second, fully self aligned gate contact 6.5 third, includes buried rail track supply. The cells on...
Standard cell track height scaling has been identified as an option to provide significant area savings. A direct consequence of reduction is that the width power rails needs be reduced accommodate patterning constraints well leave sufficient tracks for routing. Narrower are highly resistive, reducing headroom near operating due IR drop, which not acceptable. For example, a 20% performance loss observed 10% supply voltage drop. To worsen situation slowdown in CPP and newer metallization...
This paper proposes TEASE (Technology Exploration and Analysis for SoC-level Evaluation), a framework to systematically analyze evaluate system design in finFET-based technology node. The proposed combines both lithography electrical constraints of particular node optimize the standard cell library performance. Growing complexity logic at nodes below 20nm causes adopt style that can embrace simplicity required enable manufacturing, along with process be finely tuned desired performance...
The density requirement expected for the 10nm node continues to increase pressure on patterning. With frontend of line adopting a regular layout (mostly unidirectional), most complexity needed functional chip ends up in interconnect layer and Metal1. Assuming that Extreme Ultra Violet Lithography (EUVL) will not be ready early stage production but only high volume manufacturing, we have studied how ArF immersion lithography can extended Metal1 sustain development technology as well phase,...
Standard cell track height scaling provides us with sufficient area at the standard library level. The efficiency of this technique and complexities involved method have been discussed in detail [1,2]. However, benefits diminish when we consider incorporating on-chip power grid into DTCO exploration loop. We previously outlined several layout techniques to improve utilization density technology [2,4]. proposed only minimize impact on design. In work, discuss need combine 3D – μTSV logic...
Field-programmable gate arrays (FPGA) are drawing increasing interest because of its performance, power consumption and configurability. They execute wide range parallelizable algorithms which changes in accordance to variations wireless channel statistics utilized smart antenna array embedded systems. In this article, we've described the FPGA implementation a QRD processor that enables run-time definition input matrix dimensions. The design employs mixture CORDIC-based processing (array...
Partition of monolithic 2D (M2D) chip and heterogeneous integration resultant chiplets are inevitable in the near future due to rising cost transistor complexity process. 3D stacking is required maintain tight cross-IP communication fit into limited footprint over Printed Circuit Board (PCB). We discuss criteria choice for 3DIC technology flavor logic chiplet scaling knobs terms optimized key performance indicators (KPI) at system level.