A5005194074- Parallel Computing and Optimization Techniques
- Interconnection Networks and Systems
- 3D IC and TSV technologies
- VLSI and FPGA Design Techniques
- Electromagnetic Compatibility and Noise Suppression
- Advanced DC-DC Converters
- Low-power high-performance VLSI design
- Advanced Battery Technologies Research
- Multilevel Inverters and Converters
- Advanced Data Storage Technologies
- Embedded Systems Design Techniques
- Analog and Mixed-Signal Circuit Design
- Climate variability and models
- Tropical and Extratropical Cyclones Research
- Meteorological Phenomena and Simulations
- Neural Networks and Reservoir Computing
- CCD and CMOS Imaging Sensors
- Cloud Computing and Resource Management
- Microgrid Control and Optimization
- Optical Network Technologies
- Distributed and Parallel Computing Systems
- Electronic Packaging and Soldering Technologies
- Photonic and Optical Devices
- Traffic control and management
- Gyrotron and Vacuum Electronics Research
Qualcomm (United States)
2018-2023
Texas Instruments (India)
2006-2023
Texas Instruments (United States)
2023
Marymount University
2021
Market Matters
2018-2020
University of California, San Diego
2011-2020
National Institute of Technology Warangal
2020
Kakatiya University
2016-2019
Qualcomm (United Kingdom)
2019
National Institute of Technology Tiruchirappalli
2011
Historically, server designers have opted for simple memory systems by picking one of a few commoditized DDR products. We are already witnessing major upheaval in the off-chip hierarchy, with introduction many new products—buffer-on-board, LRDIMM, HMC, HBM, and NVMs, to name few. Given plethora choices, it is expected that different vendors will adopt strategies their high-capacity systems, often deviating from standards and/or integrating functionality within systems. These likely differ...
In this paper, we describe CACTI-IO, an extension to CACTI that includes power, area, and timing models for the IO PHY of OFF-chip memory interface various server mobile configurations. CACTI-IO enables design space exploration along with dynamic random access cache parameters. We added four case studies use study tradeoffs between capacity, bandwidth (BW), power. The show helps to: 1) provide power numbers can be fed into a system simulator accurate calculations; 2) optimize configurations...
2.5-D integration technology is gaining attention and popularity in manycore computing system design. systems integrate homogeneous or heterogeneous chiplets a flexible cost-effective way. The design choices of impact overall performance, manufacturing cost, thermal feasibility. This article proposes cross-layer co-optimization methodology for systems. We jointly optimize the network topology chiplet placement across logical, physical, circuit layers to improve reduce lower operating...
Photonic network-on-chip (PNoC) is a promising candidate to replace traditional electrical NoC in manycore systems that require substantial bandwidths. The photonic links the PNoC comprise laser sources, optical ring resonators, passive waveguides, and photodetectors. Reliable link operation requires sources resonators have matching frequencies. However, inherent thermal sensitivity of devices manufacturing process variations can lead frequency mismatch. To avoid this mismatch, micro-heaters...
We present a flash ADC design technique that compensates for static nonlinearity of the up-front track-and-hold circuit, so high speed and linearity can be obtained at same time. The proposed functions in synergy with new background comparator offset correction scheme. excess quantization noise generated due to autozero process is derived. demonstrate efficacy our techniques measurement results 160 MSPS 6-bit converter designed 0.35- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML"...
The conventional power network design process requires iterative modifications to the existing eliminate hot spots and converge target impedance parameters. At later stages in IC process, this procedure may require significant time human resources due limited flexibility accommodate necessary changes. Power delivery exploration during early of bring considerable savings system development effort. number iterations be greatly reduced by choosing initial parameters sufficiently close optimum....
Power Delivery Network (PDN) is a critical component in modern System-on-Chip (SoC) designs. With the rapid development applications, quality of PDN, especially Package (PKG) determines whether sufficient amount power can be delivered to computing blocks. In conventional PKG design, PDN design typically takes multiple weeks including many manual iterations for optimization. Also, there large discrepancy between (i) quick simulation tools used assessment during phase, and (ii) golden...
2.5D integration technology is gaining popularity in the design of homogeneous and heterogeneous many-core computing systems. network design, both inter- intra-chiplet, impacts overall system performance as well its manufacturing cost thermal feasibility. This paper introduces a cross-layer methodology for designing networks We optimize chiplet placement jointly across logical, physical, circuit layers to achieve an energy-efficient network, while maximizing performance, minimizing cost,...
We describe CACTI-IO, an extension to CACTI [4] that includes power, area and timing models for the IO PHY of off-chip memory interface various server mobile configurations. CACTI-IO enables design space exploration along with DRAM cache parameters. added three case studies use study tradeoffs between capacity, bandwidth power.
The board-level power network design process is governed by system-level parameters such as the number of layers and ball grid array (BGA) pattern. These influence characteristics resulting system, power, speed, cost. Evaluating impact these is, however, challenging. To estimate reduction in impedance if, for example, additional BGA balls are dedicated to delivery adjustments board layout an extraction required. processes poorly automated, requiring significant time labor. Automating...
The board-level power network design process is governed by system-level parameters, such as the number of layers and ball grid array (BGA) pattern. These parameters influence characteristics resulting system, power, speed, cost. Evaluating impact these however challenging. To estimate reduction in impedance if, for example, additional BGA balls are dedicated to delivery adjustments board layout, an extraction required. processes poorly automated, requiring significant time labor. Automating...
A variety of interconnect technologies and standards (DIMMs, MCP, POP, stacked-die 3D-stack) enable a controller IC to communicate with an external SDRAM, or multiple SDRAMs over shared interconnect. Low-power requirements have driven mobile controllers mobile-SDRAM (LPDDR) memory solutions. However, LPDDR configurations do not scale match the throughput capacity processors, emerging tablet products that bring new divergent tradeoffs among subsystem metrics. As result, identifying...
A variety of interconnect technologies and standards (DIMMs, MCP, POP, stacked-die 3D-stack) enable a controller IC to communicate with an external SDRAM, or multiple SDRAMs over shared interconnect. Low-power requirements have driven mobile controllers mobile-SDRAM (LPDDR) memory solutions. However, LPDDR configurations do not scale match the throughput capacity processors, emerging tablet products that bring new divergent tradeoffs among subsystem metrics. As result, identifying...
Many-core chip architectures are now feasible, but the power consumption of electrical networks-on-chip does not scale well. Silicon photonic NoCs (PNoCs) more scalable and efficient, floorplan optimization is challenging. Prior work optimizes PNoC floorplans through simultaneous place route, address cross-layer effects that span optical boundaries, thermal profiles, or job scheduling policies. This paper proposes a comprehensive, silicon core cluster floorplan. Our placement (locations...
Advancements in multi-core have created interest among many research groups finding out ways to harness the true power of processor cores. Recent suggests that on-board component such as cache memory plays a crucial role deciding performance systems. In this paper, is evaluated through parameters access time, miss rate and penalty. The influence over execution time also discussed. Results obtained from simulated studies environments with different instruction set architectures (ISA) like...
Abstract Power harvesting Wi-Fi detectors Networks structure the dream of web things frameworks. Vitality reaping hubs might be sent deliberately to screen at least one targets along with a valuable resource. Be that as it may, these depend on surrounding vitality assets sun oriented, they experience irregular power appearances. Subsequently, may debilitate their collected force simultaneously observing an objective. To this quit, network administrators require tough arrangement secure all...
Partition of monolithic 2D (M2D) chip and heterogeneous integration resultant chiplets are inevitable in the near future due to rising cost transistor complexity process. 3D stacking is required maintain tight cross-IP communication fit into limited footprint over Printed Circuit Board (PCB). We discuss criteria choice for 3DIC technology flavor logic chiplet scaling knobs terms optimized key performance indicators (KPI) at system level.
Over the past decades, aggressive voltage scaling combined with increased power demands has placed stringent requirements on on-chip quality. Unwanted fluctuations and droops may cause a variety of issues, ranging from glitch to device malfunction. If revealed at later stages design process, mitigation techniques become unbearably costly in both time money. A framework for exploratory delivery optimization is described enhance network during early process accordance specifications. The...
3D interconnect between two dies can span a wide range of bandwidths and region areas, depending on the application, partitioning dies, die size, floorplan. We explore concept dividing such an into local clusters, each with cluster clock. combine clustering choice three clock synchronization schemes (synchronous, source-synchronous, asynchronous) study impacts power, area timing tree, data path 3DIO. build model for as function key system requirements constraints: total bandwidth, area,...
Unlike the routing of on-chip power delivery networks which is a highly automated process, board-level nets usually performed manually. The process complicated by geometric and electrical constraints that impose restrictions on process. An algorithm presented here provides efficient generation refinement network geometries at layout level. In case study, path connecting management integrated circuit to ball grid array routed using tool, producing low impedance while complying with metal...
The way of analyzing, designing and building real-time projects has been changed due to the rapid growth internet, mobile technologies intelligent applications. Most these applications are intelligent, tiny distributed components called as agent. Agent works like it takes input from numerous sources gives back response. In this paper how agents can be implemented in vehicle traffic management especially large cities identifying various challenges when there is a population vehicles. our...