As combinations of signoff corners grow in modern SoCs, minimization clock skew variation across is important. Large can cause difficulties multi-corner timing closure because fixing violations at one corner lead to other corners. Such "ping-pong" effects significant power and area overheads time signoff. We propose a novel framework encompassing both global local network optimizations minimize the sum variations different PVT between all sequentially adjacent sink pairs. The optimization...

Clock power, skew and maximum latency are three key metrics for clock distribution in low-power high-performance designs. An H-tree offers minimum good robustness against variations, but at the cost of large wirelength power. On other hand, a "fishbone" network with spine-ribs structures has smaller wirelength, larger skew, as compared to an H-tree. No previous work enables systematic exploration regime between spine achieve optimal tradeoff among latency. In this paper, we study concept...

The Prim-Dijkstra (PD ) construction [1] was first presented over 20 years ago as a way to efficiently trade off between shortest-path and minimum-wirelength routing trees. This approach has stood the test of time, having been integrated into leading semiconductor design methodologies electronic automation tools. PD optimizes conflicting objectives wirelength (WL) source-sink pathlength (PL) by blending classic Prim Dijkstra spanning tree algorithms. However, this work shows, can sometimes...

Continued technology scaling with more pervasive use of multi-patterning has led to complex design rules and increased difficulty maintaining high layout densities. Intuitively, emerging constraints such as unidirectional patterning or via spacing will decrease achievable density the final place-and-route solution, worsening die area product cost. However, no methodology exists for accurate assessment rules' impact on physical chip implementation. At same time, this is a crucial need early...

Technology scaling to 10nm and below introduces complex intra-row inter-row constraints in standard-cell detailed placement. Examples of such are found rules for drain-drain abutment, minimum implant region area width, oxide diffusion (OD) notching jogging, etc. Typically, these too the normal global-detailed placement flow fully consider. On other hand, guardbanding library cell design so that arbitrary adjacencies all "correct by construction" has increasingly high cost. This motivates...

The clock trees of high-performance synchronous circuits have many logic cells (e.g., gating cells, multiplexers and dividers) in order to achieve aggressive required performance across a wide range operating modes conditions. As result, tree structures become very complex difficult optimize with automatic synthesis (CTS) tools. In advanced process nodes, CTS becomes even more challenging due on-chip variation (OCV) effects. this paper, we present new methodology that optimizes cell...

Aggressive pitch scaling in sub-10nm nodes has introduced complex design rules which make routing extremely challenging. Cell architectures have also been changed to meet the rules. For example, metal layers below M1 are used gain additional resources. New cell wherein inter-row is allowed force consideration of vertical alignment cells. In this work, we propose a mixed-integer linear programming (MILP)-based, detailed placement optimization maximize direct utilization for congestion and...

Self-aligned multiple patterning (SAMP), due to its low overlay error, has emerged as the leading option for 1D gridded back-end-of-line (BEOL) in sub-14nm nodes. To form actual routing patterns from a uniform "sea of wires", cut mask is needed line-end cutting or realization space between segments. Constraints on shapes and minimum spacing result end-of-line (EOL) extensions non-functional (i.e. dummy fill) patterns; resulting capacitance timing changes must be consistent with signoff...

Technology scaling to 10nm and below introduces complex intra-row inter-row constraints in standard-cell detailed placement. Examples of such are found rules for drain-drain abutment, minimum implant region area width, oxide diffusion (OD) notching jogging, etc. Typically, these too the normal global-detailed placement flow fully consider. On other hand, guardbanding library cell design so that arbitrary adjacencies all correct by construction has increasingly high cost. This motivates...

In sub-10nm, nodes, a change or step in diffusion height between adjacent standard cells causes yield loss as well form of model-hardware miscorrelation called neighbor effect (NDE). Cell libraries must inevitably have multiple heights (numbers fins PFETs and NFETs) order to enable flexible exploration the power-performance envelope for design. However, this brings step-induced risks NDE, which guardbanding is costly, loss. Special filler can protect against harmful NDE effects, but are...

In sub-10nm, nodes, a change or step in diffusion height between adjacent standard cells causes yield loss as well form of model-hardware miscorrelation called neighbor effect (NDE). Cell libraries must inevitably have multiple heights (numbers fins PFETs and NFETs) order to enable flexible exploration the power-performance envelope for design. However, this brings step-induced risks NDE, which guardbanding is costly, loss. Special filler can protect against harmful NDE effects, but are...

Aggressive resolution enhancement techniques such as inverse lithography (ILT) often lead to complex, non-rectilinear mask shapes which make writing extremely slow and expensive. To reduce shot count of complex shapes, writers allow overlapping shots, due the problem fracturing with minimum is NP-hard. The need correct for e-beam proximity effect makes even more challenging. Although a number heuristics have been proposed, there has no systematic study analyze quality their solutions. In...

In advanced technology nodes, BEOL interconnect stack geometry has become a key lever for design enablement. The rapid increase of RC leads to not only performance loss from delay increase, but circuit power and area degradation as well. Thus, optimization dimensions (i.e., wire width, spacing thickness subject given layers pitch constraint) is crucial achieve better product performance, area. However, it obvious how optimize dimensions, especially in sub-10nm nodes. this work, we study by...

Signal delay uncertainty induced by crosstalk is a critical challenge to the physical design of long interconnect channels in DRAM products at 2× and 1× technology nodes. Due severe cost challenges high-volume, commodity market, layout resources including channel width, buffers, number metal routing layers are extremely scarce. We describe new optimizer that reduces crosstalk-induced uncertainty, weighted signal criticality aware activity correlations (e.g., reduce mutual shielding). Instead...

This paper presents novel level-up shifters called Dual Step Level-up Shifter (DSLS) and Stacked (SDSLS) which are simpler, yet more efficient than conventional shifters. We compare the proposed designs with two existing designs: a shifter Contention-Mitigated Level (CMLS). The delay of is less that CMLS by up to 4.86% 6.51%, respectively. power consumption 6.68% 5.40%, DSLS SDSLS act as gating circuit well shifter. Thus, we conclude our very effective for low designs.

Reducing power consumption in a processor using multiple supply voltages is commonly adopted mobile embedded systems. Level shifters are crucial components such systems to interface two modules operating with different voltage levels. In this paper, we propose low and high performance level-up called dual step shifter (DSLS) stacked (SDSLS). DSLS has buffer structure improve the speed circuit size over conventional as well by avoiding contention. SDSLS proposed further for utilizing...

3D interconnect between two dies can span a wide range of bandwidths and region areas, depending on the application, partitioning dies, die size, floorplan. We explore concept dividing such an into local clusters, each with cluster clock. combine clustering choice three clock synchronization schemes (synchronous, source-synchronous, asynchronous) study impacts power, area timing tree, data path 3DIO. build model for as function key system requirements constraints: total bandwidth, area,...

3D logic-logic integration is an important future lever for continued cost and density scaling value propositions in the semiconductor industry. In 3DIC context, several works have proposed "mix-and-match" of multiple stacked die, according to binning information, improve overall product yield. However, each die these independently designed: there no holistic "design eventual stacking" any die. Separately, many approaches been design partitioning implementation with including stacked-die...

Aggressive resolution enhancement techniques such as inverse lithography (ILT) often lead to complex, nonrectilinear mask shapes which make writing extremely slow and expensive. To reduce shot count of complex shapes, writers allow overlapping shots, due the problem fracturing with minimum is NP-hard. The need account for e-beam proximity effect makes even more challenging. Although a number heuristics have been proposed, there has no systematic study analyze quality their solutions. In this...

Cost and skew are among the most fundamental objectives for interconnect tree synthesis. The cost-skew tradeoff is particularly important in buffered clock construction, where subnets an "sweet spot" balancing on-chip variation-aware analysis, skew, power other factors. In advanced nodes, both performance critical to IC products, there a renewed challenge of minimizing wirelength while controlling skew. this work, we formulate minimum-cost bounded spanning Steiner problems as flow-based...

Aggressive resolution enhancement techniques such as inverse lithography (ILT) often lead to complex, non-rectilinear mask shapes which make writing extremely slow and expensive. To reduce shot count of complex shapes, writers allow overlapping shots, due the problem fracturing with minimum is NP-hard. The need correct for e-beam proximity effect makes even more challenging. Although a number heuristics have been proposed, there has no systematic study analyze quality their solutions. In...

Both the capacity and complexity of modern FPGA devices increase rapidly. Also, it is common that battery-powered embedded systems are equipped with devices. Therefore, reducing power consumption has become a very crucial issue. Not only dynamic but also leakage increases as feature size to manufacture shrinks. To reduce devices, carbon-nanotube field effect transistor (CNFET) emerged promising candidate for replacing silicon metal oxide semiconductor (Si-MOSFET). In this paper, we propose...

Self-aligned multiple patterning, due to its low overlay error, has emerged as the leading option for 1-D gridded back-end-of-line (BEOL) in sub-14-nm nodes. To form actual routing patterns from a uniform “sea of wires,” cut masks are needed line-end cutting or realization space between segments. The results nonfunctional (i.e., dummy fill) that change wire capacitance, and hence design timing power. Therefore, remove such fill patterns, extra 2-D block used. However, cannot arbitrary rule...