Partitioning of circuit netlists in VLSI design is considered. It shown that the second smallest eigenvalue a matrix derived from netlist gives provably good approximation optimal ratio cut partition cost. also demonstrated fast Lanczos-type methods for sparse symmetric problem are robust basis computing heuristic cuts based on eigenvector this eigenvalue. Effective clustering an immediate by-product computation and very successful difficult input classes proposed CAD literature. The...

As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting cores. With power now first-order design constraint, early-stage estimation of NoC has become crucially important. ORION [29] was amongst first models released, and since been fairly widely used NoCs. However, when validated against recent prototypes -- Intel 80-core Teraflops chip Scalable Communications Core (SCC) we saw significant deviation that can lead to erroneous...

As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting cores. With power now first-order design constraint, early-stage estimation of NoC has become crucially important. ORION was amongst first models released, and since been fairly widely used NoCs. However, when validated against recent prototypes - Intel 80-core Teraflops chip communications core (SCC) we saw significant deviation that can lead to erroneous choices. This...

Approximation can increase performance or reduce power consumption with a simplified inaccurate circuit in application contexts where strict requirements are relaxed. For applications related to human senses, approximate arithmetic be used generate sufficient results rather than absolutely accurate results. Approximate design exploits tradeoff of accuracy computation versus and power. However, required varies according applications, 100% still some situations. In this paper, we propose an...

There has been increased research interest in systems composed of multiple autonomous mobile robots exhibiting collective behavior. Groups are constructed, with an aim to studying such issues as group architecture, resource conflict, origin cooperation, learning, and geometric problems. As yet, few applications robotics have reported, supporting theory is still its formative stages. In this paper, the authors give a critical survey existing works discuss open problems field, emphasizing...

Historically, server designers have opted for simple memory systems by picking one of a few commoditized DDR products. We are already witnessing major upheaval in the off-chip hierarchy, with introduction many new products—buffer-on-board, LRDIMM, HMC, HBM, and NVMs, to name few. Given plethora choices, it is expected that different vendors will adopt strategies their high-capacity systems, often deviating from standards and/or integrating functionality within systems. These likely differ...

As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting cores. With power now first-order design constraint, early-stage estimation of NoC has become crucially important. In this work, we present ORION 2.0, an enhanced and area simulator, which offers significant accuracy improvement relative to its predecessor, 1.0.

This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize state-of-the-art after two decades research recursive bisection and implement a new placer, called Capo, to empirically study achievable limits approach. From among recently proposed improvements bisection, Capo incorporates leading-edge multilevel min-cut partitioner [7], techniques for partitioning with small tolerance [8], optimal partitioners end-case min-wirelength placers...

The deferred-merge embedding (DME) algorithm, which embeds any given connection topology to create a clock tree with zero skew while minimizing total wirelength, is presented. algorithm always yields exact trees respect the appropriate delay model. Experimental results show an 8% 15% wire length reduction over some previous constructions. DME may be applied either Elmore or linear model, and optimal wirelength for delay. very fast running in time number of synchronizing elements. A unified...

Elmore delay has been widely used to estimate interconnect delays in the performance-driven synthesis and layout of very-large-scale-integration (VLSI) routing topologies. For typical RLC interconnections, however, can deviate significantly from SPICE-computed delay, since it is independent inductance rise time input signal. Here, we develop an analytical model based on first second moments incorporate effects into for interconnection lines under step input. Delay estimates using our are...

The International Technology Roadmap for Semiconductors (ITRS) is a collaborative effort within the semiconductor industry to confront challenges implicit in Moore's law. roadmap's goal present an industry-wide consensus on "best current estimate" of its R&D needs out 15-year horizon. As such, ITRS provides guide efforts companies, research organizations, and governments improve quality investment decisions made at all levels. 2001 notable because it was developed with truly international...

Digital system designs are the product of valuable effort and know-how. Their embodiments, from software HDL program down to device-level netlist mask data, represent carefully guarded intellectual property (IP). Hence, design methodologies based on IP reuse require new mechanisms protect rights producers owners. This paper establishes principles watermarking-based protection, where a watermark is mechanism for identification that (i) nearly invisible human machine inspection, (ii) difficult...

The deferred-merge embedding (DME) algorithm is presented. In linear time, it embeds any given connection topology into the Manhattan plane to create a clock tree with zero skew while minimizing total wirelength. Experimental results show that yields exact trees 9% 16% wirelength reduction over previous constructions. DME may be applied either Elmore or delay model and optimal for delay.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Digital system designs are the product of valuable effort and know-how. Their embodiments, from software hardware description language program down to device-level netlist mask data, represent carefully guarded intellectual property (IP). Hence, design methodologies based on IP reuse require new mechanisms protect rights producers owners. This paper establishes principles watermarking-based protection, where a watermark is mechanism for identification that is: (1) nearly invisible human...

A fast approach to the minimum rectilinear Steiner tree (MRST) problem is presented. The method yields results that reduce wire length by up 2% 3% over previous methods, and first heuristic which has been shown have a performance ratio less than 3/2; in fact, or equal 4/3 on entire class of instances where c(MST)/c(MRST) exactly 3/2. algorithm practical asymptotic complexity owing an elegant implementation uses methods from computation geometry parallelizes readily. randomized variation...

The authors propose a provably good performance-driven global routing algorithm for both cell-based and building-block design. approach is based on new bounded-radius minimum tree formulation. first present several heuristics with performance, an analog of Prim's spanning construction. Next, they give which simultaneously minimizes cost the longest interconnection path, so that are bounded by small constant factors away from optimal. They also show geometry helps in routing: Manhattan plane,...

Recent work has illustrated the promise ofmultilevel approaches for partitioning large circuits. Multilevel partitioningrecursively clusters instance until its size is smallerthan a given threshold, then unclusters while applyinga refinement algorithm. Our multilevel partitioner usesa new technique to control number of levels in matching-basedclustering phase and also exploits recent innovations classiciterative partitioning. heuristic outperforms numerousexisting bipartitioning heuristics,...

Automated cell placement is a critical problem in very large scale integration (VLSI) physical design. New analytical methods that simultaneously spread cells and optimize wirelength have recently received much attention from both academia industry. A novel simple objective function for spreading over the area described patent of Naylor et al. (U.S. Pat. 6301693). When combined with function, this allows efficient simultaneous optimization using nonlinear techniques. In paper, we implement...

The Nesterov's method approach to analytic placement has recently demonstrated strong solution quality and scalability. We dissect the previous implementation strategy show that can be significantly improved using two levers: 1) constraint-oriented local smoothing 2) dynamic step size adaptation. propose a new density function comprehends overflow of area resources; this enables at per-bin granularity. Our adaptation automatically determines effectively allocates optimization effort improve...

Modern digital IC designs have a critical operating point, or “wall of slack”, that limits voltage scaling. Even with an error-tolerance mechanism, scaling below - so-called overscaling results in more timing errors than can be effectively detected corrected. This the effectiveness trading off system reliability and power. We propose design-level approach to (power) in, e.g., microprocessor designs. increase range values at which (timing) error rate is acceptable; we achieve this through...