The Nesterov's method approach to analytic placement has recently demonstrated strong solution quality and scalability. We dissect the previous implementation strategy show that can be significantly improved using two levers: 1) constraint-oriented local smoothing 2) dynamic step size adaptation. propose a new density function comprehends overflow of area resources; this enables at per-bin granularity. Our adaptation automatically determines effectively allocates optimization effort improve...

In this article, we propose an automated standard cell synthesis framework, SP&R, which simultaneously solves P&R without deploying any sequential/separate operations, by a novel dynamic pin allocation scheme. The proposed SP&R utilizes the multiobjective optimization feature of satisfiability modulo theories (SMT) to obtain optimal layouts. To achieve practical scalability develop various search-space reduction techniques, including breaking symmetry, conditional assignment/localization,...

We design an algorithmic framework using matrix exponentials for time-domain simulation of power delivery network (PDN). Our can reuse factorized matrices to simulate the large-scale linear PDN system with variable stepsizes. In contrast, current conventional solvers have use fixed step-size approach in order generated by expensive decomposition. Based on proposed exponential integration framework, we a solver R-MATEX flexible time-stepping capability. The key operation and vector product...

As pin accessibility encounters more challenges due to the less number of tracks, higher density, and complex design rules, routability has become one bottleneck sub-10nm designs. Thus, we need a new methodology for fast turnaround in analyzing feasibility layout architecture, e.g., rules patterns assignment. In this paper, propose novel framework that efficiently identifies rule-correct by creating well-organized formulation. We start with SAT-friendly ILP formulation which satisfies...

We propose a flat, analytic, mixed-size placement algorithm ePlace-3D for three-dimension integrated circuits (3D-ICs) using nonlinear optimization. Our contributions are (1) electrostatics based 3D density function with globally uniform smoothness (2) numerical solution improved spectral formulation (3) pre-conditioner convergence acceleration (4) interleaved 2D-3D efficiency enhancement. placer outperforms the leading work mPL6-3D and NTUplace3-3D 6.44% 37.15% shorter wirelength, 9.11%...

Standard cell synthesis requires careful engineering approaches to ensure routability across various digital IC designs since physical design (PD) for sub-7nm technology nodes demands holistic efforts address urgent and nontrivial challenges. The smaller number of routing tracks more complex rules due the sophisticated multi-patterning make place-and-route (P&R) designing a standard extremely hard time-consuming. Many conventional have been suggested improving transistor-level P&R pin...

Pin accessibility encounters nontrivial challenges due to the smaller number of routing tracks, higher pin density, and more complex design rules. Consequently, securing rule-correct routability has become a critical bottleneck for sub-10-nm IC designs (particularly in detailed stage) costing days runtime. To reduce turnaround time, designers demand new methodologies analyze feasibility given layout architecture (e.g., conditional rules, assignment patterns, etc). There are several...

We propose an efficient algorithmic framework for time-domain circuit simulation using exponential integrators. This work addresses several critical issues exposed by previous matrix based research, and makes it capable of simulating stiff nonlinear system at a large scale. In this framework, the system's nonlinearity is treated with Rosenbrock-Euler formulation. The vector product computed invert Krylov subspace method. Our proposed method has distinguished advantages over conventional...

Routability diagnosis has increasingly become the bottleneck in detailed routing for sub-10nm technology due to limited tracks, high density, and complex design rules. The conventional ways examine routability of are ILP- SAT-based techniques. However, once we identify routability, remains an open problem physical designers. In this paper, propose a novel framework, called ROAD, which diagnoses explicit reasons failures. proposed ROAD framework utilizes diagnosis-friendly SAT formulation...

In this work, we propose a matrix exponential-based time-integration algorithm for dynamic analysis of power delivery network (PDN) with nonlinear components. The presented method is an explicit and very competitive applications compared to traditional low order approximation methods, such as backward Euler Newton-Raphson iterations (BE). proposed takes comparable number time steps complete the whole simulation. Second, only one LU decomposition per step while BE requires at least two...

This paper presents a non-contact electrocardiogram (ECG) measurement platform that compensates for motion-induced impedance changes via interdigitated electrode channels in concert with software reconstruction algorithms. Specifically, the of is non-invasively acquired real-time by exploiting custom designed two independent featuring transfer functions are used to reconstruct motion-compensated ECG waveforms. The developed validated on human subjects, illustrating up 76.3% improvement over...

Many-tier vertical gate-all-around nanowire FET (VFET) synthesis strongly demands a holistic approach of modeling/formulating/optimizing transistor placement and in-cell routing to obtain the maximum-achievable power, performance, area, cost (PPAC) benefits. In this article, we propose novel satisfiability modulo theories (SMT)-based many-tier VFET standard cell (SDC) framework that simultaneously solves place-and-route (P&R). We devise an extended relative positioning constraint dummy gate...

Built-in self-test (BIST) is a well-known design technique in which part of circuit used to test the itself. BIST plays an important role for embedded memories, do not have pins or pads exposed toward periphery chip testing with automatic equipment. With rapidly increasing number memories modern SOCs (up hundreds each hard macro SOC), product designers incur substantial costs time (subject possible power constraints) and logic physical resources (area, routing, power). However, only limited...

Testability of ECO logic is currently a significant bottleneck in the SOC implementation flow. Front-end designers sometimes require large functional ECOs close to scheduled tapeout dates or for later design revisions. To avoid loss test coverage, flip-flops must be added into existing scan chains with minimal increase time and impact on routing timing slack. We address new Incremental Multiple-Scan Chain Ordering problem formulation automate tedious time-consuming process stitching ECOs....

Built-in self-test (BIST) is a well-known design technique in which part of circuit used to test the itself. BIST plays an important role for embedded memories, do not have pins or pads exposed toward periphery chip testing with automatic equipment. With rapidly increasing number memories modern SOCs (up hundreds each hard macro SOC), product designers incur substantial costs time (subject possible power constraints) and logic physical resources (area, routing, power). However, only limited...

Built-in self-test (BIST) is a well-known design technique in which part of circuit used to test the itself. BIST plays an important role for embedded memories, do not have pins or pads exposed toward periphery chip testing with automatic equipment. With rapidly increasing number memories modern SOCs (up hundreds each hard macro SOC), product designers incur substantial costs time (subject possible power constraints) and logic physical resources (area, routing, power). However, only limited...

Three-dimensional integrated circuit (3D IC) technology offers a potential breakthrough to enable paradigm-shift strategy, called “more than Moore,” with novel features and advantages over the conventional 2D process technology. By having three-dimensional interconnections, 3D IC provides substantial wirelength reduction massive amount of bandwidth, which gives significant performance improvement overcome many nontrivial challenges in semiconductor industry. Moreover, integration enables...

Accurate analysis of power delivery network is indispensable to assess VLSI package and interconnection network. Given the S-parameters that characterize linear packaging system, we derive transient response networks. We utilize compressed sensing technique generate impulse fits with sparsity. Our method shows accurate, concise, stable results.

With the relentless scaling of technology nodes, physical design engineers encounter non-trivial challenges caused by rapidly increasing complexity, particularly in routing stage. Back-end designers must manually stitch/modify all rule violations (DRVs) that remain after automatic place-and-route (P&R), during implementation engineering change orders (ECOs). In this paper, we propose CoRe-ECO, a concurrent refinement framework for efficient automation ECO process. Our efficiently resolves...

Tree structures and algorithms provide a fundamental powerful data abstraction methods for computer science operations research. In particular, they enable significant advancement of IC physical design techniques optimization. For the last half century, Prof. T. C. Hu has areas in science, including network flows, integer programming, shortest paths, binary trees, global routing, etc. this article, we select summarize three important interesting tree-related topics (ancestor column...

Data/algorithmic representations of 3D floorplans for integrated circuits is an essential problem in the study VLSI circuits. Given a fixed number rectangular blocks and their volume, floorplan describe orientations positions relative to origin three dimensional space. In our study, we 1). present analyze novel representation call corner links, 2). give new analysis partial order representation, 3). discuss equivalence two provide algorithms mutual reducibility, inspect several key properties.

Testability of ECO logic is currently a significant bottleneck in the SOC implementation flow. Front-end designers sometimes require large functional ECOs close to scheduled tapeout dates or for later design revisions. To avoid loss test coverage, flip-flops must be added into existing scan chains with minimal increase time and impact on routing timing slack. We address new Incremental Multiple-Scan Chain Ordering problem formulation automate tedious time-consuming process stitching ECOs....

Innovations and advancements on physical design (PD) in the past half century significantly contribute to progresses of modern VLSI designs. While ``Moore's Law'' ``Dennard Scaling'' have become slowing down recently, society encountered a set challenges opportunities. This article is presented at event Life Time Achievement Award for Dr. Satoshi Goto by ISPD 2017. Goto's career designs sets an exemplar role model young engineers. Thus, we use his contributions as thread describe our...