A5001763918- 3D IC and TSV technologies
- Electronic Packaging and Soldering Technologies
- Thin-Film Transistor Technologies
- Semiconductor materials and devices
- Silicon and Solar Cell Technologies
- Additive Manufacturing and 3D Printing Technologies
- Silicon Nanostructures and Photoluminescence
- Nanofabrication and Lithography Techniques
- Advanced Surface Polishing Techniques
- Integrated Circuits and Semiconductor Failure Analysis
- Copper Interconnects and Reliability
- Carbon Nanotubes in Composites
- Nanowire Synthesis and Applications
- Advancements in Semiconductor Devices and Circuit Design
- Electrodeposition and Electroless Coatings
- Semiconductor Lasers and Optical Devices
- Diamond and Carbon-based Materials Research
- Adhesion, Friction, and Surface Interactions
- Manufacturing Process and Optimization
- Semiconductor materials and interfaces
- Graphene research and applications
- Advanced Welding Techniques Analysis
- Advancements in Photolithography Techniques
- Solidification and crystal growth phenomena
- CCD and CMOS Imaging Sensors
IMEC
2015-2024
KU Leuven
2014-2020
Delft University of Technology
2006-2016
Intel (United States)
2015
Japan External Trade Organization
2009-2010
University of Tehran
2002-2006
A silicon photodiode detector is presented for use in scanning electron microscopy (SEM). Enhanced imaging capabilities are achieved sub-keV energy values by employing a pure boron (PureB) layer technology to deposit nanometer-thin photosensitive anodes. As result, using backscattered electrons demonstrated 50-eV landing values. The built up of several closely packed photodiodes, and obtain high speed, each engineered with low series resistance capacitance (<; 3 pF/mm <sup...
Pure boron (PureB) chemical-vapor deposition performed at 400°C is applied as a postmetalization process module to fabricate near-ideal p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> n photodiodes with nm-thin PureB-only beam-entrance windows. The have near-theoretical sensitivity and high stability for optical characterization either UV light down wavelength of 270 nm or low-energy electrons 200 eV.
In this paper a bump-less process is introduced in order to further scale down the pitch of microbumps. Electrical resistance measurement, Cross section SEM and mechanical characterizations show successful 3D stacking using proposed method.
Abstract This paper reports on 3D phase field simulations of IMC growth in Co/Sn and Cu/Sn solder systems. In agreement with experimental micrographs, we obtain uniform the CoSn 3 joints a non-uniform wavy morphology for Cu 6 Sn 5 joints. Furthermore, were performed to an insight impact grain size, boundary versus bulk diffusion, IMC/Sn interface mobility kinetics. It is found that diffusion or have limited evolution. A obtained when relatively large compared interface, while mobilities are...
In this paper we report the monolithic integration of two single grain silicon layers for SRAM and image sensor applications. A 12 × 28 lateral photodiode array with a 25_μm pixel size prepared on top three transistor readout circuit individual outputs every is demonstrated. 6T cells stacked transistors were to compare performance area each cell in different configurations.
Envisioning wide future relevance, work is reviewed here on the pure dopant deposition of boron (PureB), gallium (PureGa) and combination two (PureGaB), as used in fabrication nanometer shallow p + n Si and/or Ge diodes. Focus placed special properties that have put these diodes a class apart: their ideal electrical behavior together with electrical, optical chemical robustness lead to cutting-edge application photodiodes for detecting low-penetration-depth beams, example EUV lithography...
In this paper, we report monolithic integration of two single-grain silicon layers for static random access memory (SRAM) and image sensor applications. A 12 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\times$</tex></formula> 28 lateral photodiode array with a 25- Notation="TeX">$\mu\hbox{m}$</tex></formula> pixel size prepared on top three-transistor readout circuit individual outputs every is...
For the application of carbon nanotubes (CNT) as interconnects in integrated circuits low temperature vertically aligned growth with a high tube density is required. We found that etching and cleaning steps used semiconductor technology can damage catalyst or support layer, preventing CNT growth. propose to use lift-off process sacrificial layer prevent damage. Using this method we created electrical measurement structures for bundles. The bundles grown at 500°C display resistivity good...
In this paper, spacer bumps concept is introduced to increase the process window for TCB, lower sensitivity of electrical yield bump height variation, maintain gap between two dies and prevent too much solder deformation a test vehicle having multi-diameter from 40um down 5um pitches. Adding improves dramatically close 100% ensures good joint IMC formation both face N=2 back N=4 stacks.
Vertical stacking of transistors is a promising technology which can realize compact and high-speed integrated circuits (ICs) with short interconnect delay increased functionality. Two layers low-temperature fabricated single-grain thin-film (SG TFTs) have been monolithically integrated. Using finite element method (FEM) simulation, the damage to bottom layer devices during laser crystallization top silicon has investigated. N-channel metal–oxide–semiconductor (n-MOS) mobilities are 565 393...
We review our achievement in monolithic 3D-ICs based on single-grain Si TFTs that are fabricated inside a with low-temperature process. With pulsed-laser crystallization, grains diameter of 6 μm successfully formed predetermined positions. Single-grain (SG) the mobility for electron and holes 600 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs 200 /Vs, respectively. Using two layers SG TFT layers, CMOS inverter, 6T-SRAM image...
In this paper a reflow process for fine-pitch micro-bumps is studied. A mathematical model the proposed and verified by experimental measurements. The influence of profile parameters on shape micro-bumps, will be discussed using three commercial ovens. Furthermore, measurement results bump height variations after over 300mm wafer presented.
In this paper,the wettability, quality of joint formation and electrical yield daisy chains in 3D stacks when using Cobalt Nickel as UBM with different finish layers such immersion Au, ELD NiB, Cu SAM are investigated. The performance the characterized by cross-section SEM images, EDS analysis resistance measurement chains.
This paper introduces a method for direct electrodeposition of indium on superconducting (SC) layers with an optimized electrolyte. Indium-to-indium bump and indium-to-SC bonding is achieved using plated wafers. An atmospheric plasma cleaning process removes native oxide, thermocompression (TCB) developed at air, enabling successful In-In In-SC different microbumps pitch. Plasma-treated bumps exhibit high applicability flip chip low temperatures in air atmosphere, as confirmed by...
In this paper, direct die-to-wafer (D2W) hybrid bonding flow is explored using plasma diced dies with bond pad pitch scaling down to 2 μm. All the die preparation steps (including backside thinning, dicing, surface activation, and pick-and-place) are proposed demonstrated on carrier wafers minimize defects at of enable thin handling capability. With flexible shape design (chamfered corners) can be realized, inspection results show well-defined edge clean sidewall. Good Kelvin daisy chain...
In this paper, for first time, damascene process on thinned and bonded device wafer to a carrier using TBM layer is introduced. All the BS steps including, dielectric depositions, etching, seed/barrier deposition, plating CMP are performed at temperatures within thermal budget of layer. FIB images show no impact processing FS bumps. This done test vehicle with 20, 10, 7 5um pitch structures in F2F B2F (or F2B) forms, where good electrical data, solder joint formation reliability performance obtained.
The effect of external mechanical stress on the crystallization amorphous silicon deposited thin, flexible glass substrates has been studied. A 5–10 Å, layer nickel surface acted as seed and was observed to initiate at top proceed down towards substrate. Application a tensile during annealing stage led uniform, partial for temperatures low 310 °C. In contrast, application compressive buckling films under nonuniform over sample. crystalline quality investigated using scanning electron...
In this paper we report results and challenges of replacing Cu with Co as UBM (under bump metallization) in microbumps for 3D technology applications. Cobalt has softer single IMC (intermetallic compounds) according to calculations using can reduce consumption material by solder which is attractive sub 10um pitches microbumps. However, cobalt oxidizes very fast poor wetting shown Figure 1. This shows two SEM images cross section 20um (left) 50um (right) from IMEC test vehicles where...