A5006376684- Radiation Effects in Electronics
- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Advancements in Semiconductor Devices and Circuit Design
- VLSI and Analog Circuit Testing
- Low-power high-performance VLSI design
- Silicon Carbide Semiconductor Technologies
- Electrostatic Discharge in Electronics
- Physical Unclonable Functions (PUFs) and Hardware Security
- Advanced Memory and Neural Computing
- Laser Design and Applications
- Ga2O3 and related materials
- Spectroscopy and Laser Applications
- Silicon and Solar Cell Technologies
- Photonic and Optical Devices
- GaN-based semiconductor devices and materials
- Radiation Detection and Scintillator Technologies
- Advanced Machining and Optimization Techniques
- Belt Conveyor Systems Engineering
- Nonlinear Optical Materials Studies
- Scientific Measurement and Uncertainty Evaluation
- Advancements in Photolithography Techniques
- Electric Power Systems and Control
- Radiation Shielding Materials Analysis
- Electric and Hybrid Vehicle Technologies
Vanderbilt University
2016-2025
Kirtland Air Force Base
2003
Fraunhofer Institute for Physical Measurement Techniques
1983-1987
Lawrence Livermore National Laboratory
1979
Heavy ion irradiation was simulated using a Geant4 based Monte-Carlo transport code. Electronic and nuclear physics were used to generate statistical profiles of charge deposition in the sensitive volume an SEU hardened SRAM. Simulation results show that materials external can affect experimentally measured cross-section curve.
Heavy ion-induced single-event burnout (SEB) is investigated in high-voltage silicon carbide power MOSFETs. Experimental data for 1200-V SiC MOSFETs show a significant decrease SEB onset voltage particle linear energy transfers greater than 10 MeV/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg, above which the threshold nearly constant at half of rated maximum operating these devices. TCAD simulations parasitic bipolar junction...
Heavy-ion data suggest that a common mechanism is responsible for single-event burnout (SEB) in 1200-V power MOSFETs and junction barrier Schottky (JBS) diodes. Similarly, heavy-ion also leakage current degradation both devices. This mechanism, based on ion-induced, highly localized energy pulses, demonstrated simulations shown to be capable of causing SEB the JBS
A novel mechanism for upset is seen in a commercially available 0.25 /spl mu/m 10-T SEE hardened SRAM cell. Unlike traditional multiple node charge collection which diffusions near single event strike collect the deposited carriers, this new involves direct drift-diffusion at an NFET transistor conjunction with parasitic bipolar conduction nearby PFET transistors. The compromise design, thus causing upsets. was identified using laser testing and three-dimensional TCAD simulations.
Three-dimensional TCAD models are used in mixed- mode simulations to analyze the effectiveness of well contacts at mitigating parasitic PNP bipolar conduction due a direct hit ion strike. 130 nm and 90 technology simulated. Results show careful contact design can improve mitigation. However, is seen decrease from simulations.
Heavy-ion microbeam and broadbeam data are presented for a 65 nm bulk CMOS process showing the existence of pulse quenching at normal angular incidence designs where pMOS transistors in common n-wells or isolated separate n-wells. Experimental simulations show that is more prevalent n-well design than design, leading to significantly reduced SET pulsewidths cross-section design.
Heavy-ion experimental results were used to characterize single-event upset trends in 16 nm bulk FinFET, 20 planar, and 28 planar D flip-flops. Experimental data show that FinFET flip-flops have considerably lower SEU cross sections than their sub-32 counterparts for linear energy transfer (LET) less 10 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg. However, section improvement compared the technologies is weak high LET...
Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions 14-nm FinFETs. Minimal radiation-induced voltage shift across a variety transistor types is observed. Off-state leakage current nMOSFET transistors exhibits strong gate dependence, indicating electrostatic control sub-fin region corresponding parasitic conduction path largest concern for radiation hardness in FinFET technology. The high-...
Low-energy ion-induced breakdown and single-event burnout (SEB) are experimentally observed in beta-gallium oxide ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -Ga2O3) Schottky diodes with voltages well below those of expected electrical breakdown. Fundamentally different responses were among alpha particle, Cf-252, heavy-ion irradiation. Technology computer-aided...
A well-collapse source-injection mode for SRAM SEU is demonstrated through TCAD modeling. The recovery of the SRAM's state shown to be based upon resistive path from p+ -sources in well. Multiple cell upset patterns direct charge collection and mechanisms are predicted compared test data.
<?Pub Dtl=""?> The total ionizing dose (TID) response of bulk FinFETs is investigated for various geometry variations, such as fin width, channel length, and pitch. buildup oxide-trapped charge in the shallow trench isolation turns on a parasitic transistor, leading to increased leakage current (higher <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${{I}_{{\rm OFF}}}$</tex></formula> .) TID-induced...
A set of upset criteria based on circuit characteristic switching time frame is developed and used to bridge transistor-level TCAD simulations circuit-level single-event (SE) cross sections for advanced (fast small) digital circuits. Interpretation the measured 3D simulated (SEU) responses bulk planar circuits FinFET using short-time quantitatively explains observed divergence low-LET from simple geometric scaling predictions. Comparisons computed section show excellent agreement.
Ion- and terrestrial neutron-induced single-event burnout (SEB) data indicate that a thicker, more lightly doped epitaxial (epi) region significantly increases the threshold at which ion-induced SEB occurs in silicon carbide (SiC) power MOSFETs junction barrier Schottky (JBS) diodes. Simulations reduction of dissipation along core ion track is responsible for increased robustness devices have higher breakdown voltage ratings. Implications circuit design show using 3300-V MOSFET provides...
Experimental heavy-ion responses of silicon carbide (SiC) junction barrier Schottky (JBS) diodes are presented. Measured data indicate that heavy ions having range less than the epitaxial thickness do not cause degradation or catastrophic failure, even with device biased above rated breakdown voltage. also when have longer layer thickness, devices exhibit as single-event leakage current (SELC), well burnout (SEB) at biases half Device failure was observed irradiating high-energy long ranges,...
Single-event burnout (SEB) is experimentally observed in structurally improved vertical Beta-gallium oxide ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -Ga2O3) Schottky barrier diodes (SBDs) with Pt/PtOx contacts and high-k field-plate (FP) dielectrics. These SBDs are resistant to alpha particle strikes up the in-air reverse bias voltage of 475 V, but SEB-induced...
Simulations show that neglecting ion-ion interaction processes (both particles having Z>1) results in an underestimation of the total on-orbit single event upset error rate by more than two orders magnitude for certain technologies. The inclusion nuclear reactions leads to dramatically different SEU rates CMOS devices containing high Z materials compared with direct ionization primary ion alone. Device geometry and material composition have a dramatic effect on charge deposition small...
Direct observation of fast-transient single event signatures often involves considerable uncertainty due to the limitations monitoring circuitry. A built-in-self-test circuit for measurement single-event transients (SET) has been implemented in a 45 nm partially depleted silicon-on-insulator technology that allows extraction measurement-induced uncertainty. SET pulse width data from heavy-ion experiments are provided and compared computer aided design simulations. method compensating bias...
Cross sections and failure in time rates for neutron-induced single-event burnout (SEB) are estimated SiC power MOSFETs using a method based on combining results from heavy ion SEB experimental data, 3-D TCAD prediction of sensitive volumes, Monte Carlo radiation transport simulations secondary particle production. The agree well with data useful understanding the mechanisms data.
For advanced technology nodes, the close proximity of semiconductor regions results in multiple collecting charge after an ion strike. This is especially true for static random access memory (SRAM) integrated circuits (ICs) where transistors are placed closer to each other compared application-specific ICs (ASICs). As a result, SRAM highly vulnerable multi-cell upsets (MCU). In this work, heavy-ion irradiations bulk 28-nm planar and 16-nm FinFET investigated show that small cell size node...