To address the large energy dissipation of our current computing architecture, nonvolatile voltage-gate-assisted spin-orbit-torque (VGSOT) MRAM combines advantages (SOT) and voltage control magnetic anisotropy (VCMA) systems. Here authors study VGSOT writing with perpendicular tunnel junctions, show it to be reliable, low error rate resilience intensive stresses. The spin Hall angle VCMA coefficient allow 30-nm junctions. A multipillar design is suggested, high density close 2-terminal...

The increased complexity of CMOS transistor processing has led to limited scaling high density SRAM cell at advanced technology nodes. STT-MRAM appears be a promising candidate for replacing last level caches (LLC). This paper addresses design co-optimization (DTCO) and analyzes its viability as LLC (compared SRAM) the performance computing (HPC) domain (while maintaining constraint occupying merely 43.3% macro area identical capacities). is first study that breaks down power, (PPA)...

Spin Orbit Torque (SOT) magnetic random-access memory (MRAM) offers the possibility to realize ultra-high-speed Non-Volatile technology without endurance issues that plague its more mature counterpart, STT-MRAM, but at cost of density. Based on our SOT-MRAM data, we explore different bit-cell architectures through extensive Design Technology Co-optimization (DTCO) evaluate most pareto-optimum solutions for High-Density [HD] and High-Performance [HP] design full macro embedded domain. Our...

Transformers are a class of machine learning models that have piqued high interest recently due to multitude reasons. They can process multiple modalities efficiently and excellent scalability. Despite these obvious advantages, training large is very time-consuming. Hence, there been efforts speed up the using efficient distributed implementations. Many different types parallelism identified be employed standalone or in combination. However, naively combining parallelization schemes incur...

We propose, for the first time, an indium gallium zinc oxide (IGZO)-based 2T1C compute cell (IGZO-cell) analog in-memory computing. To assess impact of IGZO-cell-based array including periphery on power and accuracy, a PyTorch framework was developed to analytically modeled components. The results are reported ResNet20 network Canadian Institute For Advanced Research-10 (CIFAR-10) benchmark. state-of-the-art energy efficiency 15 peta operations per second (POPS)/W is achieved by using our...

The increased metal resistance degrades both the performance and write margin of SRAM circuits in sub-10nm nodes. This paper utilizes buried power distribution as ability booster 3nm node. BPR-SRAM offers up to 34.5% read speed 498.6mV improvement over conventional SRAM. Gem5 system simulator predicts 28.2% gain with server-processor having L2 L3 cache compared baseline.

We present a detailed study of the impact damage minimizing patterning schemes on electrical performance perpendicular STT-MRAM devices at array level, compatible with 22 nm CMOS technology node. By employing novel scheme involving physical ion beam etch (IBE), etchback and oxidation steps, we show reduction in switching voltage (32%), energy (20%) an improvement reliability window (20%), as compared to conventional etch. These improvements are reported conjunction 10-year data retention...

Spin Torque Transfer Magnetic RAM (STT-MRAM) is a promising Non-Volatile Memory (NVM) technology achieving high density, low leakage power, and relatively small read/write delays. It provides solution to improve the performance mitigate power consumption compared SRAM-based processors. However, process heterogeneity sophisticated back-end-of-line (BEOL) structure make it difficult integrate STT-MRAM in two-dimensional integrated circuits (2D ICs). In this article, we implement RISC-V-based...

Spin-transfer torque magnetic random access memory (STT-MRAM) based computation-in-memory (CIM) architectures have shown great prospects for an energy-efficient computing. However, device variations and non-idealities narrow down the sensing margin that severely impacts computing accuracy. In this work, we propose adaptive referencing mechanism to improve of a CIM architecture boolean binary logic (BBL) operations. We generate reference signals using multiple STT-MRAM devices place them...

Due to the complexity of device processing, trade-off between yield and area has resulted in diminishing rate scaling for high-density static random access memory (SRAM) cell at advanced CMOS nodes. An introduction extreme ultraviolet (EUV) multipatterning added additional cost technology order realize 3-D structure ultrascaled metal routing. In this era, spin-transfer torque (STT)-MRAM can provide an alternative SRAM last level cache (LLC) applications. article, we discuss design tradeoff...

Hierarchical very-large-scale integration (VLSI) flows are an understudied yet critical approach to achieving design closure at giga-scale complexity and gigahertz frequency targets. This paper proposes a novel hierarchical physical flow enabling the building of high-density commercial-quality two-tier face-to-face-bonded 3D ICs. We significantly reduce associated manufacturing cost compared existing implementation and, for first time, achieve competitiveness against 2D reference in large...

Since Non-Volatile Memory (NVM) technologies are being explored extensively nowadays as viable replacements for SRAM based memories in LLCs and even L2 caches, we try to take stock of their potential level 1 (L1) data caches. These NVMs like Spin Torque Transfer RAM(STT-MRAM), Resistive-RAM(ReRAM) Phase Change RAM (PRAM) not subject leakage problems with technology scaling. They also show significant area gains lower dynamic power consumption. A direct drop-in replacement by is, however,...

STT-MRAM is a promising candidate to replace SRAM in Last Level Caches (LLCs) thanks its high density and reduced leakage. However, write delay, energy, defects risk of breakdown have hindered widespread adoption. To address these challenges, the bitcell bias conditions need be co-optimized. We present Design Technology Co-optimization (DTCO) strategy for LLC eSTT-MRAM based on new defects-aware stochastic framework, calibrated an experimental MTJ array applied 5 nm 3 nodes FinFET core...

STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) has attracted considerable attention of late since it is the most promising logic compatible nonvolatile memory that suitable for advanced nodes (N28 and beyond) in terms endurance, speed power. Embedded thus been proposed as a candidate emerging low standby-power connectivity systems such IoT (Internet-of-Things) wearables. We utilize high performance CoFeB based perpendicular MTJ (pMTJ) device to realize power highly dense array...

Monolithic 3-D IC (M3-D) is a promising solution to improve the performance and energy-efficiency of modern processors. But, designers are faced with challenges in design tools methodologies, especially for power thermal verifications. We developed new physical flow that optimally places routes cache modules one tier logic gates other. Our tool also builds high-quality clock delivery networks targeting logic-on-memory M3-D designs. Finally, we sign-off analysis evaluate power, performance,...

IGZO (InGaZnO)-DRAM has been increasingly explored as an alternative to traditional DRAM due its reduced transistor leakage (∼10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−18</sup> A) and related minimal storage node capacitance in addition ease of integration (entirely BEOL). The 2TOC IGZO-DRAM bit-cell configuration additional benefits from a scaling point view the potential for monolithic 3D stacking. We present based Capacitor-less...

This paper analyzes the most feasible 3D integration and partitioning scheme for STT-MRAM based caches in an advanced Mobile SoC on process demonstration of first ever functional integrated STT devices. We present schemes from a design -architecture perspective Power Performance Area (PPA) analysis is carried out 2D designs with both SRAM caches. Our work shows that PPA benefits Memory Logic are magnified when it can be exploited to accommodate larger general. also show partitioned exploit...

As the technology scaling advances, limitations of traditional memories in terms density and energy become more evident. Modern caches occupy a large part CPU physical size high static leakage poses limit to overall efficiency systems, including IoT/edge devices. Several alternatives CMOS SRAM have been studied during past few decades, some which already represent viable replacement for different levels cache hierarchy. One most promising technologies is spin-transfer torque magnetic RAM...

This paper presents the Design Technology Co-optimization (DTCO) study of 1-diode 1- Voltage controlled magnetic anisotropy (1D-1VCMA) stack, which functions as Storage Class Memory (SCM) to bridge gap between DRAM and flash memory. The dual requirement low sneak current high non-linearity for bidirectional selectors in 1S-1R crossbar memories is extremely challenging achieve practically. Moreover, IR drop due parasitic resistance (RPAR) results significant degradation voltage across memory...

This paper presents an extensive study of 6T-SRAM based on FinFET for advanced technology nodes beyond 5nm. We deduce that parasitic resistance becomes the main bottleneck SRAM design at these nodes. SRAM's writing margin and read speed are impacted due to increased Bit-Line (BL) Word-Line (WL) resistance. work primarily explores two possible solutions improve process nodes: 1) strapping BL WL higher metal, 2) adopting optimized BEOL. Strapping metal layer improves Write Trip Point (WTP) by...

Current main memory organizations in embedded and mobile application systems are DRAM dominated. The ever-increasing gap between today's processor speeds makes the subsystem design a major aspect of computer system design. However, limitations to scaling other challenges like refresh provide undesired trade-offs performance, energy area be made by architecture designers. Several emerging NVM options being explored at least partly remedy this but today it is very hard assess viability these...

SRAM based memory systems are plagued by a number of problems like sub-threshold leakage and susceptibility to read/write failure with dynamic voltage scaling schemes or low supply voltage. Non-Volatile Memory (NVM) technologies being explored extensively nowadays replace the conventional memories even for level 1 (L1) caches. These NVMs Spin Torque Transfer RAM (STT-MRAM), Resistive-RAM (ReRAM) Phase Change (PRAM) less hindered technology consume lesser area. However, simple replacement is...