A5056611420- 3D IC and TSV technologies
- Interconnection Networks and Systems
- Embedded Systems Design Techniques
- VLSI and FPGA Design Techniques
- Semiconductor materials and devices
- Parallel Computing and Optimization Techniques
- Real-Time Systems Scheduling
- Manufacturing Process and Optimization
- VLSI and Analog Circuit Testing
- Low-power high-performance VLSI design
- Advanced Memory and Neural Computing
- Plasma Diagnostics and Applications
- Advancements in Semiconductor Devices and Circuit Design
- Advancements in Photolithography Techniques
- Additive Manufacturing and 3D Printing Technologies
- Electronic Packaging and Soldering Technologies
- Distributed and Parallel Computing Systems
- 3D Surveying and Cultural Heritage
- Distributed systems and fault tolerance
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Data Storage Technologies
- CCD and CMOS Imaging Sensors
- Error Correcting Code Techniques
- Neural Networks and Applications
- Archaeological Research and Protection
IMEC
2015-2024
Université Libre de Bruxelles
2012-2024
Vrije Universiteit Brussel
2022
Max Planck Society
2014-2017
Max Planck Institute for Plasma Physics
2014-2017
Max Planck Institute for Plasma Physics - Greifswald
2017
KU Leuven
2011-2016
International Medical Equipment Collaborative
2016
Imec the Netherlands
2015
Qualcomm (United States)
2009
The paper presents an improved method for the deinterleaving of radar signals, based on a time arrival analysis and use sequential difference histogram (SDIF) determining pulse repetition interval (PRI). optimal detection threshold in SDIF is derived, which greatly contributes to efficiency algorithm. algorithm applied classic, frequency-agile staggered PRI signals. It shown that new very successful high-pulse-density environments complex signal types. Special attention given application...
These last years, we have witnessed a dramatic increase in the number of cores available computational platforms. Concurrently, new coding paradigm dividing tasks into smaller execution instances called threads, was developed to take advantage inherent parallelism multiprocessor However, only few methods were proposed efficiently schedule hard real-time multi-threaded on multiprocessor. In this paper, propose techniques optimizing processors needed such sporadic parallel with constrained...
A nonequilibrium model is developed for the prediction of two-dimensional flow, electron and heavy particle temperatures, number density distributions in cascaded arcs monatomic gases. The system strongly coupled elliptic partial differential equations describing plasma flow solved by a numerical method based on control volume with nonstaggered grid. applied computation both stagnation flowing argon arc plasmas. results show that nearly local thermal equilibrium (LTE), except very close to...
A multiprocessor scheduling algorithm named U-EDF, was presented in [1] for the of periodic tasks with implicit deadlines. It claimed that U-EDF is optimal (i.e., it can meet all deadlines every schedulable task set) and extensive simulations showed a drastic improvement number preemptions migrations comparison to state-of-the-art algorithms. However, there no proof its optimality not designed schedule sporadic tasks. In this work, we propose generalization deadlines, prove optimality....
2.5D "Chiplet" approaches allow for a dense integration of independently designed & fabricated ICs. However, this inherently adds significant interconnect latency, therefore limiting the application to latency-tolerant applications. This added latency can be eliminated by introducing "3D-SoC" design approach. is an extension highly successful 2D System-on-Chip (SoC) methodology, where system automatically partitioned into separate chips that are concurrently interconnected in 3 <sup...
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores data memory units widely different sizes. interconnect the IPs these heterogeneous platforms, Networks-on-Chip (NoC) have been proposed as an efficient scalable alternative to shared buses. NoCs can provide throughput latency guarantees by establishing virtual circuits between source destination. State-of-the-art currently exploit...
We present an IR-drop analysis of hybrid bonded 3D-ICs Power Delivery Network with backside metals and buried power rail. Two different options for the to frontside connectivity are included: μTSVs nTSVs (respectively 0.5μm, 0.09μm diameter 1Ω, 10Ω nominal resistance). Further, Hybrid Bonding CuPads used deliver second die in stack. A commercial tool is extended support both TSV pads structures, tackle inter-die on-die delivery challenges. L1 cache memory implemented on top a core as test...
In this paper, backside power delivery network (BS-PDN) and a high density 2.5D Mimcap (Metal-insulator-metal capacitor) are applied to improve dynamic IR-drop of 2D 3D ICs at sub-2nm node. An on-chip PDN design IR drop modelling framework is proposed calibrated with the physical results 64-bit low CPU. The IC various integration then PDN. used here was manufactured optimized capacitance ~70 fF/um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
We present local & global SRAM macro optimizations for 3nm FinFET and 2nm Nanosheet using Face-to-Face (F2F) Wafer-to-Wafer (W2W) hybrid bonding at sub 1um pitch. Bonding pad parasitics are measured experimentally to calibrate RC models of the used evaluate 3D-optimized memory delays. 3Doptimized macros designed reduce external delay by ~50%. With customized BEOL, performance improvement up 70% larger memories is observed compared with 2D macro. also show that bit-cell tech-level have minor...
Abstract-Over the past two decades, numerous optimal scheduling algorithms for real-time systems on multiprocessor platforms have been proposed Liu & Layland task model. However, recent studies showed that even if can theoretically schedule any feasible set, suboptimal usually perform better when executed real computation platforms. This be explained by runtime overheads such induce. We observed all current online are (completely or partially) based notion of fairness. The respect this...
We propose a power-efficient many-core server-on-chip system with 3D-stacked Wide I/O DRAM targeting cloud workloads in datacenters. The integration of on top logic die increases available memory bandwidth by using dense and fast Through-Silicon Vias (TSVs) instead off-chip IOs, enabling faster data transfers at much lower energy per bit. demonstrate methodology that includes full-system microarchitectural modeling rapid virtual physical prototyping emphasis the thermal analysis. Our...
In this paper, we address the power-aware scheduling of sporadic constrained-deadline hard real-time tasks using dynamic voltage scaling upon multiprocessor platforms. We propose two distinct algorithms. Our first algorithm is an off-line speed determination mechanism which provides identical for each processor. That guarantees that all deadlines are met if jobs scheduled EDF. The second on-line and adaptive adjustment reduces energy consumption while system running.
In this paper, we develop physical design tools and methodologies to tackle the inter-tier performance variations caused by low temperature manufacturing in 2-tier gate-level monolithic 3D ICs (M3D). First, model top tier front-end-of-line (FEOL) device mobility degradation its impact on cell delay/power values. Next, quantify of tungsten interconnect cost-driven metal layer saving back-end-of-line (BEOL) bottom tier. These models are used our new full-chip M3D flow named Derated 2D. This...
Spin Torque Transfer Magnetic RAM (STT-MRAM) is a promising Non-Volatile Memory (NVM) technology achieving high density, low leakage power, and relatively small read/write delays. It provides solution to improve the performance mitigate power consumption compared SRAM-based processors. However, process heterogeneity sophisticated back-end-of-line (BEOL) structure make it difficult integrate STT-MRAM in two-dimensional integrated circuits (2D ICs). In this article, we implement RISC-V-based...
In this paper we study power, performance, and cost (PPC) tradeoffs for 2-tier, gate-level, full-chip GDS monolithic 3D ICs (M3D) built using a foundry-grade 7nm bulk FinFET technology. We first develop highly-accurate wafer die models 2D M3D to PPC tradeoffs. our study, both designs are optimized in terms of the number BEOL metal layers used routing obtain best possible values. new CAD methodology 2-tier gate-level M3D, named Projected Flow, that allows us accurately compare RC parasitics...
In this work, we explore the resource of backside (BS) interconnect for signal routing in SRAM macro and logic at 2nm technology node to tackle scaling induced frontside (FS) BEOL congestion challenge. High-aspect ratio nano-Through-Silicon-Vias (nTSVs) used as BS FS metal layers connections have been manufactured with sufficiently low resistance (~20 Ohm) capacitance (~0.04fF). Compared BEOL, is very beneficial improving delay power efficiency long routing. Performance improvement up 44%...
Hierarchical very-large-scale integration (VLSI) flows are an understudied yet critical approach to achieving design closure at giga-scale complexity and gigahertz frequency targets. This paper proposes a novel hierarchical physical flow enabling the building of high-density commercial-quality two-tier face-to-face-bonded 3D ICs. We significantly reduce associated manufacturing cost compared existing implementation and, for first time, achieve competitiveness against 2D reference in large...
New technologies for manufacturing 3D Stacked ICs offer numerous opportunities the design of complex and effcient embedded systems. But these also introduce many options at system/chip level, hard to grasp during complete cycle. Because sequential nature current practices, designers are often forced margins meet required specications, resulting in sub-optimal designs. In this paper we new methodology practical tool chain, called PathFinding Flow, that can help easily trade-off between...
In this paper, we present thermal and mechanical characterization of a DRAM-on-logic stack. Our experimental data indicates that holistic optimization design technology is needed to achieve working 3D stacks. Particularly, the stack organization TSV/μbump layout must be fine-tuned together with for managing challenges. order support system designers, propose hereto dedicated model, integrated into flow. We also indicate required from foundries OSATs good fidelity measurement results.
We present extensions to commercially available EDA tools support Wafer-to-Wafer (W2W), Face-to-Face (F2F), hybrid bonding 3D integration with ~1μm pitch Cupad structures. Proposed flow is based on Innovus™ Place & Route (P&R) tool from Cadence Design Systems and allows functional system partitioning user specified information automated netlist split. Due fine pitch, the can occur at lower levels of hierarchy, resulting in significant number pins die-crossing critical paths. has been...
We present a study on detection of buried anti-personnel mines (APM) by means infrared imaging. First, an analytical theoretical thermal model is presented. Then we describe original approach towards the simulation extended and summarize results. These are then compared with results obtained from experiments in laboratory real environment conditions. In order to use whole dynamic information contained image sequences, two methods for extracting difference temperature response between objects...