This paper describes a novel design methodology to implement secure DPA resistant crypto processor. The is suitable for integration in common automated standard cell ASIC or FPGA flow. technique combines building blocks make 'new' compound cells, which have close constant power consumption. Experimental results indicate 50 times reduction the consumption fluctuations.

This paper describes a novel design methodology to implement secure DPA resistant crypto processor. The is suitable for integration in common automated standard cell ASIC or FPGA flow. technique combines building blocks make 'new' compound cells, which have close constant power consumption. Experimental results indicate 50 times reduction the consumption fluctuations.

Security-critical products rely on the secrecy and integrity of their cryptographic keys. This is challenging for low-cost resource-constrained embedded devices, with an attacker having physical access to integrated circuit (IC). Physically, unclonable functions are emerging technology in this market. They extract bits from unavoidable IC manufacturing variations, remarkably analogous unique human fingerprints. However, post-processing by helper data algorithms (HDAs) indispensable meet...

We present a lightweight PUF-based authentication approach that is practical in settings where server authenticates device, and for use cases the number of authentications limited over device's lifetime. Our scheme uses server-managed challenge/response pair (CRP) lockdown protocol: unlike prior approaches, an adaptive chosen-challenge adversary with machine learning capabilities cannot obtain new CRPs without server's implicit permission. The faced problem deriving PUF model amount training...

RFID (Radio Frequency IDentification) tags need to include security functions, yet at the same time their resources are extremely limited. Moreover, provide privacy, authentication and protection against tracking of without loosing system scalability, a public-key based approach is inevitable, which shown by M. Burmester et al. In this paper, we present an architecture state-of-the-art processor for with Elliptic Curve (EC) over GF(2^163). It shows plausibility meeting both efficiency...

This paper presents the architecture of a fully pipelined AES encryption processor on single chip FPGA. By using loop unrolling and inner-round outer-round pipelining techniques, maximum throughput 21.54 Gbits/s is achieved. A fast an area efficient composite field implementation byte substitution phase designed optimum number pipeline stages for FPGA implementation. achieved 84 block RAMs 5177 slices VirtexII-Pro with latency 31 cycles per rate 4.2 Mbps/Slice.

This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s throughput at 56 mW power consumption in a 0.18-μm CMOS standard cell technology. integrated circuit implements Rijndael algorithm, any combination block lengths (128, 192, or 25 bits) key 256 bits). We present architecture discuss optimizations. also measurement results were obtained from set 14 test samples this chip.

RFID-tags are a new generation of bar-codes with added functionality. An emerging application is the use for anti-counterfeiting by embedding them into product. Public-key cryptography (PKC) offers an attractive solution to counterfeiting problem but whether publickey cryptosystem can be implemented on RFID tag or not remains unclear. In this paper, we investigate which PKC-based identification protocols useful these applications. We also discuss feasibility based elliptic curve (ECC) and...

This paper studies and evaluates the extent to which automated compiler techniques can defend against timing-based side-channel attacks on modern x86 processors. We study how processors leak timing information through side-channels that relate control flow data flow. To eliminate key-dependent behavior related flow, we propose use of if-conversion in a backend, evaluate proof-of-concept prototype implementation. Furthermore, demonstrate two ways programs lack cache still implementations such...

This paper explores the area-throughput trade-off for an ASIC implementation of Advanced Encryption Standard (AES).Different pipelined implementations AES algorithm as well design decisions and area optimizations that lead to a low high throughput encryption processor are presented.With loop unrolling outer-round pipelining techniques, throughputs 30 Gbits/s 70 achievable in 0.18-m CMOS technology.Moreover, by composite field byte substitution phase (inner-round pipelining), consumption is...

In this paper we propose the idea of using soft decision information in helper data algorithms (HDA). We derive and verify a distribution for responses SRAM-based physically unclonable functions (PUFs) show that becomes available without loss min-entropy fuzzy secret. This significantly improves implementation overhead an SRAM PUF + HDA cryptographic key generation compared to previous constructions.