A5049908114- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Integrated Circuits and Semiconductor Failure Analysis
- Oral microbiology and periodontitis research
- Dental materials and restorations
- Dental Erosion and Treatment
- Dental Trauma and Treatments
- Dental Health and Care Utilization
Capital Medical University
2024
Intel (United States)
2005-2015
A 14nm logic technology using 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical layers, and air-gapped interconnects at performance-critical layers is described. The feature rectangular fins 8nm fin width 42nm height, 4 xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> generation high-k metal gate, 6 strained...
A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance is presented. Transistor length scaled down to while not scaling the oxide as a means improve reduce power. Increased NMOS PMOS drive currents are achieved by strain junction engineering. 193nm lithography along APSM mask used on critical provide aggressive design rules 6-T SRAM cell size 0.57/spl mu/m/sup 2/....
A 32 nm logic technology for high performance microprocessors is described. 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> generation high-k + metal gate transistors provide record drive currents at the tightest pitch reported any or 28 technology. NMOS are 1.62 mA/um Idsat and 0.231 Idlin 1.0 V 100 nA/um I <sub xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> . PMOS 1.37 0.240 The impact of SRAM cell array size on Vccmin reported.
This paper details the transistor aging and gate oxide reliability of Intel's 14nm process technology. technology introduces 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> generation tri-gate 4 xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> high-κ dielectrics metal-gate electrodes. The metrics reported here highlight gains attained through optimizations as well intrinsic challenges from device scaling.
An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented. At 1V and off current of 100nA/mum, transistors have record currents 1.21mA/mum 0.71mA/mum for NMOS PMOS respectively. This industry leading currently in high volume manufacturing