This paper presents a methodology to implement PID (proportional, integral, derivative) controllers in FPGAs (field-programmable gate arrays) using fixed-point numerical representation. The Matlab/Simulink environment is used for modeling, simulation and evaluation the performance provided by different representations given control process. A static bit-width analyzer give specialized representation each operand/operator controller system. After analysis, VHDL of system generated. Results...

Context: Exercising the implementation of an adaptive system (AS) effectively, in order to detect faults, is not a trivial task. This due characteristics this type systems, such as high number configurations and runtime adaptations. In context, characterisation challenges for testing ASs may support definition suitable strategies. However, currently spread over several studies literature. Objective: analysing testing-related which are described literature, establishing generic...

Adaptive Systems (ASs) can adapt themselves to achanging environment or new user needs. Monitors are essential in AS, being responsible for collecting and processing data from environment. There exist different kinds of monitors with distinct characteristics. Based on a literature review, we have noticed that usually designed implemented an inadequate way: i) making them obscure the source-code, ii) compelling all same polling rate also iii) predetermining execution order among them. This...

In this work aims new techniques for mapping software loops to FPGAs. Extensive and aggressive use of pipelining achieving high performance solutions is the main goal. Those are foreseen effectively take advantage hardware synergies available in current FPGA devices, especially DSP blocks on-chip configurable memories.

Context: Testing adaptive systems (ASs) is particularly challenging due to certain characteristics such as the high number of possible configurations, runtime adaptations and interactions between system its surrounding environment. Therefore, combination different testing approaches in order compose a strategy expected improve quality designed test suites. Objective: To devise experiment with for ASs that relies on particular these systems. Method: We ranked devised composed three top-ranked...

This paper describes an alternative approach to direct mapping loops described in high-level languages onto FPGAs. Different from other approaches, this technique does not inherit software pipelining techniques. The control is distributed over operations, thus a finite state machine necessary the order of allowing efficient hardware implementations. specification block done by means LALP, domain specific language specially designed help application While syntax resembles C, it contains...

This paper presents the use of LALP to implement typical industrial application kernels, ADPCM Encoder and Decoder, in FPGAs. is a domain specific language its compilation framework aims direct mapping algorithms originally described high-level onto In particular, focuses on loop pipelining, key technique for design hardware accelerators. While syntax resembles C, it contains certain constructs that allow programmer interventions enforce or relax data dependences as needed, so optimize...

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained from Application-Specific Integrated Circuits (ASICs), while still keeping design implementation flexibility. However, efficiently program FPGAs, one needs expertise of hardware developers master description languages (HDLs) such as VHDL or Verilog. The attempts furnish a high-level compilation flow (e.g., C...

Although embedded systems have been around for quite a long time, just in recent years they attracted major industry and academic interest. There is perception that computing paradigm shift taking place, so the need to provide computer science students with required expertise field. In this paper we describe our experience of using reconfigurable platform throughout number courses. By doing allow get acquired concepts practices under different contexts normal curriculum. The application...

Compiladores de síntese alto nível vem se popularizando. Esses permitem transformar códigos em hardware maneira simples e rápida. As soluções atuais geram que não exploram as técnicas permitam melhorar o pipeline hardware. Este trabalho apresenta compilador LALPC utiliza para explorar paralelismo FPGAs a partir projetos descritos linguagem C. identificar aplicar otimizações acelerar trechos baseados loops. é capaz gerar sistemas desempenho, permitindo exploração espaço projeto pelo programador.

This paper presents LALPC, a prototype high-level synthesis tool, specialized in hardware generation for loop-intensive code segments. As demonstrated previous work, the underlying components target by LALPC are highly loop pipeline execution, resulting efficient implementations, both terms of performance and resources usage (silicon area). extends functionality tool using subset C language as input to describe computations, improving usability potential acceptance technique among...