Jiwu Shu

ORCID: 0000-0002-7362-2789
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About
Contact & Profiles
Research Areas
  • Advanced Data Storage Technologies
  • Caching and Content Delivery
  • Parallel Computing and Optimization Techniques
  • Distributed systems and fault tolerance
  • Cloud Computing and Resource Management
  • Distributed and Parallel Computing Systems
  • Advanced Memory and Neural Computing
  • Cloud Data Security Solutions
  • Cryptography and Data Security
  • Algorithms and Data Compression
  • Peer-to-Peer Network Technologies
  • Privacy-Preserving Technologies in Data
  • Ferroelectric and Negative Capacitance Devices
  • Cellular Automata and Applications
  • Adversarial Robustness in Machine Learning
  • Software System Performance and Reliability
  • Software-Defined Networks and 5G
  • Semiconductor materials and devices
  • Error Correcting Code Techniques
  • Network Packet Processing and Optimization
  • Coding theory and cryptography
  • Cooperative Communication and Network Coding
  • Graph Theory and Algorithms
  • Innovative Energy Harvesting Technologies
  • Anomaly Detection Techniques and Applications

Tsinghua University
2016-2025

Xiamen University
2020-2025

Minjiang University
2023-2025

Institute of Art
2023

Center for Information Technology
2021

Institute of Computing Technology
2014

Chinese Academy of Sciences
2014

Hong Kong Polytechnic University
2001-2002

Flash memory has gained in popularity as storage devices for both enterprise and embedded systems because of its high performance, low energy reduced cost. The endurance problem flash memory, however, is still a challenge getting worse density increases with the adoption multi-level cells (MLC). Prior work addressed wear leveling data reduction, but there significantly less on using file system to improve lifetimes. Some common mechanisms traditional systems, such journaling, metadata...

10.5555/2591272.2591299 article EN File and Storage Technologies 2013-02-12

Emerging non-volatile memory (NVM) technologies enable data persistence at the main level access speeds close to DRAM. In such persistent memories, writes need be performed in strict order satisfy storage consistency requirements and correct recovery from system crashes. Unfortunately, adhering a for significantly degrades performance as it requires flushing dirty blocks CPU caches waiting their completion specified by program. This paper introduces new mechanism, called Loose-Ordering...

10.1109/iccd.2014.6974684 article EN 2014-10-01

Emerging non-volatile main memories (NVMMs) provide data persistence at the memory level. To avoid double-copy overheads among user buffer, OS page cache, and storage layer, state-of-the-art NVMM-aware file systems bypass cache which directly copy between buffer NVMM storage. However, one major drawback of existing technologies is slow writes. As a result, such direct access for all operations can lead to suboptimal system performance.

10.1145/2901318.2901324 article EN 2016-04-12

Energy harvesting is gaining more and attentions due to its characteristics of ultra-long operation time without maintenance. However, frequent unpredictable power failures from energy harvesters bring performance reliability challenges traditional processors. Nonvolatile processors are promising solve such a problem their advantage zero leakage efficient backup restore operations. To optimize the nonvolatile processor design, this paper proposes new metrics consider factors for first time....

10.1145/2744769.2747910 article EN 2015-06-02

Emerging hardware like persistent memory (PM) and high-speed NICs are promising to build efficient key-value stores. However, we observe that the small-sized access pattern in stores doesn't match with persistence granularity PMs, leaving PM bandwidth underutilized. This paper proposes an PM-based storage engine named FlatStore. Specifically, it decouples role of a KV store into log structure for volatile index fast indexing. Upon it, FlatStore further incorporates two techniques: 1)...

10.1145/3373376.3378515 article EN 2020-03-09

Memory disaggregation architecture physically separates CPU and memory into independent components, which are connected via high-speed RDMA networks, greatly improving resource utilization of databases. However, such an poses unique challenges to data indexing due limited semantics near-zero computation power at memory-side. Existing indexes supporting disaggregated either suffer from low write performance, or require hardware modification. This paper presents Sherman, a write-optimized...

10.1145/3514221.3517824 article EN Proceedings of the 2022 International Conference on Management of Data 2022-06-10

RDMA provides extremely low latency and high bandwidth to distributed systems. Unfortunately, it fails scale suffers from performance degradation when transferring data an increasing number of targets on Reliable Connection (RC). We observe that the above scalability issue has its root in resource contention NIC cache, CPU cache memory each server. In this paper, we propose ScaleRPC, efficient RPC primitive using one-sided verbs reliable connection provide scalable performance. To...

10.1145/3302424.3303968 article EN 2019-03-22

Racetrack memory is an emerging non-volatile based on spintronic domain wall technology. It can achieve ultra-high storage density. Also, its read/write speed comparable to that of SRAM. Due the tape-like structure cell, a "shift" operation introduced access racetrack memory. Thus, prior research mainly focused minimizing shift latency/energy while leveraging Yet reliability issue operation, however, not well addressed. In fact, suffers from unsuccessful due misalignment. Such problem called...

10.1145/2749469.2750388 article EN 2015-05-26

Tail latency is a critical design issue in recent storage systems. B + -tree, as fundamental building block systems, incurs high tail latency, especially when placed persistent memory (PM). Our empirical study specifies two factors that lead to such spikes: ( i ) the internal structural refinement operations (i.e., split, merge, and balance), ii interference between concurrent operations. The problem even worse concurrency meets with low write bandwidth of memory. In this paper, we propose...

10.14778/3407790.3407850 article EN Proceedings of the VLDB Endowment 2020-08-01

Persistent memory provides data persistence at main level and enables memory-level storage systems. To ensure consistency of the systems, writes need to be transactional are carefully moved across boundary between volatile CPU cache persistent memory. Unfortunately, is hardware-controlled, it incurs high overhead for programs track move blocks from being persistent. In this paper, we propose a software-based mechanism, Blurred Persistence, blur volatility-persistence boundary, so as reduce...

10.1109/msst.2015.7208274 article EN 2015-05-01

How to improve the performance of single failure recovery has been an active research topic because its prevalence in large-scale storage systems. We argue that when erasure coding is deployed a cluster file system (CFS), existing designs are limited different aspects: neglecting bandwidth diversity property CFS architecture, targeting specific code constructions, and no special treatment on load balancing during recovery. In this paper, we reconsider problem setting, propose CAR,...

10.1109/dsn.2016.37 article EN 2016-06-01

While Phase Change Memory (PCM) holds a great promise as complement or even replacement of DRAM-based memory and flash-based storage, it must effectively overcome its limit on write endurance to be reliable device for an extended period intensive use. The limited can lead permanent stuck-at faults after certain number writes, which causes some cells permanently stuck at either '0' '1'. State-of-the-art solutions apply bit inversion technique selected groups data block partitioning....

10.1145/2540708.2540745 article EN 2013-12-07

Hierarchical namespaces (directory trees) in file systems are effective indexing system data. However, the update patterns of namespace metadata, such as intensive writeback and scattered small updates, exaggerate writes to flash storage dramatically, which hurts both performance endurance (i.e., limited program/erase cycles memory) system.In this paper, we propose a reconstructable system, ReconFS, reduce metadata size while providing hierarchical access. ReconFS decouples volatile...

10.5555/2591305.2591313 article EN File and Storage Technologies 2014-02-17

As the cost-per-bit of solid state disks is decreasing quickly, SSDs are supplanting HDDs in many cases, including primary storage key-value stores. However, simply deploying LSM-tree-based stores on commercial inefficient and induces heavy write amplification severe garbage collection overhead under write-intensive conditions. The main cause these critical issues comes from triple redundant management functionalities lying LSM-tree, file system flash translation layer, which block awareness...

10.1145/3126545 article EN ACM Transactions on Embedded Computing Systems 2017-09-27

In-memory key-value (KV) caching bridges the performance gap between high-performance networks and disk devices. However, prior in-memory KV systems either consider large objects or introduce additional memory overhead. In this paper, we conduct a systematic analysis over 56 production traces, make three observations: (i) small dominate traces data accesses are highly skewed; (ii) hotness of keeps stable across days; (iii) multi-get operation that retrieves multiple from same node incurs...

10.1145/3710848.3710856 article EN 2025-02-28

10.1109/icassp49660.2025.10889816 article EN ICASSP 2022 - 2022 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) 2025-03-12

10.1109/icassp49660.2025.10888857 article EN ICASSP 2022 - 2022 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) 2025-03-12
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