A5016448886- Analog and Mixed-Signal Circuit Design
- Radio Frequency Integrated Circuit Design
- Advancements in PLL and VCO Technologies
- CCD and CMOS Imaging Sensors
- Advancements in Semiconductor Devices and Circuit Design
- Microwave Engineering and Waveguides
- Low-power high-performance VLSI design
- Advanced Power Amplifier Design
- Advanced Wireless Communication Techniques
- Sensor Technology and Measurement Systems
- Acoustic Wave Resonator Technologies
- Ultra-Wideband Communications Technology
- Photonic and Optical Devices
- Semiconductor Lasers and Optical Devices
- Ultrasound Imaging and Elastography
- Ultrasonics and Acoustic Wave Propagation
- Electromagnetic Compatibility and Noise Suppression
- Advanced Data Compression Techniques
- Advanced MEMS and NEMS Technologies
- Semiconductor materials and devices
- Digital Filter Design and Implementation
- Error Correcting Code Techniques
- Analytical Chemistry and Sensors
- Advanced Memory and Neural Computing
- Neuroscience and Neural Engineering
Fudan University
2016-2025
Shanghai Fudan Microelectronics (China)
2016-2025
State Key Laboratory of ASIC and System
2015-2024
State Laboratory
2015
Nanjing University of Posts and Telecommunications
2011
East China Normal University
2002
The rapid development of machine vision applications demands hardware that can sense and process visual information in a single monolithic unit to avoid redundant data transfer. Here, we design demonstrate enhancement chip with light-sensing, memory, digital-to-analog conversion, processing functions by implementing 619-pixel 8582 transistors physical dimensions 10 mm based on wafer-scale two-dimensional (2D) monolayer molybdenum disulfide (MoS 2 ). light-sensing function analog MoS...
<?Pub Dtl=""?> To provide wide frequency tuning range (FTR) with compact implementation area, a new inductive method is introduced in this paper for CMOS 60 GHz voltage controlled oscillator (VCO). The based on switching inductor-loaded transformer by configuring different current return-paths the secondary coil of transformer. Different from previous methods, proposed VCO topology can achieve FTR multiple sub-bands at within area only one Two VCOs are demonstrated 65 nm design targets...
This paper presents for the first time design, fabrication, and demonstration of a micromachined silicon dielectric waveguide based sub-THz interconnect channel high-efficiency, low-cost interconnect, aiming to solve long-standing intrachip/interchip problem. Careful studies loss mechanisms in proposed are carried out optimize design. Both theoretical experimental results provided with good agreement. To guide new figure merit is also defined. The insertion this prototype 6-mm-long about 8.4...
In this paper, low phase-noise, low-power, and compact oscillators are demonstrated at the millimeter-wave region based on differential transmission lines (DTLs) loaded with metamaterial resonators. There two types of resonators explored: split-ring (SRRs) complementary (CSRRs). By creating a sharp stopband resonance frequency from SRR or CSRR, backward electrical-magnetic (EM) wave is reflected to couple forward EM form standing in DTL host, which results high- <i...
This paper presents a neural network-based digital calibration algorithm for high-speed and time-interleaved (TI) ADCs. In contrast with prior methods, the proposed work features joint amplitude-dependent phase-dependent nonlinear distortion correction without prior-knowledge of ADC architecture feature. A dynamic is first used to compensate distortion. Two training optimizations, including sub-range-sample-based batch schemes recursive foreground co-calibration flow are reduce error...
This brief presents an efficient and configurable multiple-input-multiple-output (MIMO) signal detector design solution its high-speed IC implementation. can support 2 × 2/3 3/4 4 MIMO quadratic phase-shift keying/16-state amplitude modulation (QAM)/64-state QAM configurations. The detection algorithm employs early-pruned technique that reduce up to 46% node extensions in the K-Best sphere decoder while maintaining almost maximum-likelihood performance. A parallel multistage folded very...
Piezoelectric micromachined ultrasonic transducers (PMUT) are promising elements to fabricate a two-dimensional (2D) array with pitch small enough (approximately half wavelength) form and receive arbitrary acoustic beams for medical imaging. However, PMUT arrays have so far failed combine the wide, high-frequency bandwidth needed achieve high axial resolution. In this paper, polydimethylsiloxane (PDMS) backing structure is introduced into PMUTs improve device while keeping sub-wavelength (λ)...
This paper presents a high-gain D-band power amplifier (PA) fabricated with 28-nm CMOS technology for sub-terahertz frequency modulated continuous wave imaging system. It adopts two-channel combining using artificial transmission lines to absorb the parasitic capacitance of ground-signal-ground pad. The layout transistors and neutralization capacitors are optimized improve maximum stable gain, stability, robustness. Asymmetrically magnetically coupled resonators used in inter-stage input...
This paper presents three-dimensional (3D) models of high-frequency piezoelectric micromachined ultrasonic transducers (PMUTs) based on the finite element method (FEM). These are verified with fabricated aluminum nitride (AlN)-based PMUT arrays. The 3D numerical model consists a sandwiched structure, silicon passive layer, and substrate cavity. Two types parameters simulated periodic boundary conditions: (1) resonant frequencies mode shapes PMUT, (2) electrical impedance acoustic field...
This paper presents a dual-mode voltage-controlled oscillator (DMVCO) and DMVCO-based wideband frequency synthesizer for software-defined radio applications. The DMVCO allows the to leverage single-sideband (SSB) mixing, power efficient approach, high-frequency local (LO) signal generation, without need of poly-phase filter or quadrature (QVCO). When compared QVCO solution provide continuous LO signals gaps. is implemented in 0.13-μm CMOS technology, occupying an active area 2.2 mm <sup...
A 2.1-GHz dividerless PLL with low power, reference spur and in-band phase noise is introduced in this paper. new detection mechanism using aperture-phase detector (APD) phase-to-analog converter (PAC) generates an analog voltage proportion to the error between VCO, then controls current amplitude of following charge pump (CP). The charging discharging currents proposed CP have equal pulse width small locked state, which reduces power consumption effectively. Moreover, compared conventional...
This brief presents a time-interleaved SAR assisted pipeline ADC with an inter-stage ring amplifier as energy efficient structure. Ring amplifiers, alternative to operational transconductance feature low power consumption and large output swing. Due non-dominant poles in the three-stage structure, conventional amplifiers suffer from bandwidth-limited settling. A bias-enhanced is proposed, which shifts higher frequencies accelerates signal In addition, 1.5-bit per comparison scheme adopted...
The paper presents a machine-learning based calibration scheme for split pipelined-SAR ADCs with open-loop residual amplifiers. Different from conventional methods, the proposed is prior-knowledge-free. adopts two-layer neural network, and directly uses bit-wise comparator results as inputs. network compensates distortion can be compressed by 75% due to network's sparsity. A 14-bit 60-MSps ADC gain boosted dynamic amplifiers fabricated in 28nm CMOS validate scheme. measurement show achieves...
This paper presents a single-coarse dual-fine architecture that improves energy-efficiency of pipelined-SAR analog-to-digital converters (ADCs). A coarse and fast sub-ADC is used to quantize the most significant bits (MSBs), which are encoded with proposed residue transformation method control generation first stages in two fine channels. The voltages generate on capacitive digital-to-analog (C-DACs) split channels directly without successive approximation processes. Therefore, conversion...
With technology scaling down to 90nm and below, many yield-driven design optimization methodologies have been proposed cope with the prominent process variation increase yield. A critical issue that affects efficiency of those methods is estimate yield when given parameters under variations. Existing either use Monte Carlo method in performance domain where thousands simulations are required, or local search parameter a number required characterize point on boundary defined by constraints....
A 14-bit 100-MS/s pipelined ADC in 0.18 mum 1P6M CMOS process is presented. new sampling technique introduced which achieves high linearity over wide bandwidth by eliminating the major sources of distortion at low and input frequencies. The uses digital background calibration, featuring a shuffled-dithering scheme, to obtain DNL +0.18/-0.18 LSB an INL +1.1/-0.6 LSB. It 85 dB SFDR 65 SNDR within first Nyquist zone, maintains 74 63 for signals up 400 MHz consumes 220 mW 1.8 V supply.
This paper presents a power-efficient, high-linearity pipelined ADC, utilizing combined front-end of the sample/hold circuit (S/H) and first multiplying digital-to-analog converter (MDAC1). In contrast with conventional merged sample-and-hold amplifier (SHA) MDAC, uses an opamp split-sharing scheme to meet different gain bandwidth requirements both S/H MDAC. mitigates memory effect without dedicated clock phase avoids crosstalk. back-end 4.5-bit opamp-sharing MDACs four-input operational...
An on-chip metamaterial resonator is demonstrated in 65 nm CMOS at 80 GHz for millimetre-wave integrated circuit (MMIC) applications. The based on a differential transmission-line (T-line) loaded with split ring (SRR), which can enhance the EM energy coupling and further improve quality factor (Q). Measurement results indicate that proposed SRR (DSRR) T-line shows sharp stopband maximum 35 dB rejection. Moreover, property of DSRR validated from measurement results. It first demonstration...
This paper presents a high-speed and low feed-through sampler with two-channel time-interleaved track-and-hold amplifiers (THAs). The THA is based on switched buffer active inductors load such that wide bandwidth in track-mode small-signal hold-mode can be both achieved within compact area. Furthermore, one clock-controlled auxiliary transistor also introduced to cancel clock hold-mode. With accurate on-chip its distribution network, double sampling rate due the structure used. chip was...
An energy-efficient dynamic comparator is presented and analyzed in this paper. The pre-amplifier dynamically powered by a floating reservoir capacitor consists of an inverter-based CMOS input pair embedded latch. power source enables common-mode voltage insensitivity the latch-embedding reduces its delay time consumption. proposed simulated 28-nm technology. It shown that energy efficiency are improved then prior preamplifier comparator. maximum clock frequency reaches 1.8 GHz, consuming...
This paper presents a 12-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems. A split-capacitor digital-to-analog (CDAC) structure is adopted reducing the core area improving sampling speed. The linearity of CDAC calibrated by programming least-significant-bits (LSBs) dummy capacitor. unit capacitor in array customized higher symmetry their mismatch. Our SAR ADC based on logic, its timing controlled...
This article presents a high-power wideband power amplifier (PA) with four-way power-combining technique for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula> -band high-resolution radar. The combiner is based on two-section Chebyshev impedance converter to achieve large bandwidth (BW) and realized slow wave coplanar waveguides (S-CPWs) reduce the insertion loss chip area....
A new 8PBF structure for 64/128 flexible point FFT processor is proposed. The processor, which based on 8*8*2 mixed radix algorithm, can deal with multiple inputs more efficiently MIMO applications. 8PFB brings the throughput of up to 1GS/s and chances register reverse down, reducing power dissipation remarkably. Meanwhile modified shift-add algorithm remove complex multipliers in processor.