In recent years, the limits of multicore approach emerged in so-called "dark silicon" issue and diminishing returns an ever-increasing core count. Hardware manufacturers, out necessity, switched their focus to accelerators, a new paradigm that pursues specialization heterogeneity over generality homogeneity. They are special-purpose hardware structures separated from CPU with aspects exhibit high degree variability. We define taxonomy based on fourteen these aspects, grouped four...

Nanophotonic is a promising solution for on-chip interconnection due to its intrinsic low-latency and low-power features. Future tiled chip multiprocessors (CMPs) rich client devices can receive energy benefits from this technology but we show that great care has be put in the integration of various involved facets avoid queuing serialization issues obtain rated potential advantages. We evaluate different management strategies accessing simple, shared photonic path (ring), working...

Optical networks-on-chip (ONoCs) are currently still in the concept stage, and would benefit from explorative studies capable of bridging gap between abstract analysis frameworks constraints challenges posed by physical layer. This paper aims to go beyond traditional comparison wavelength-routed ONoC topologies based only on their properties, for first time assesses implementation efficiency an homogeneous experimental setting practical relevance. As a result, can demonstrate significant...

Optical networks-on-chip (ONoCs) are currently still in the concept stage, and would benefit from explorative studies capable of bridging gap between abstract analysis frameworks constraints challenges posed by physical layer. This paper aims to go beyond traditional comparison wavelength-routed ONoC topologies based only on their properties, for first time assesses implementation efficiency an homogeneous experimental setting practical relevance. As a result, can demonstrate significant...

Many crossbenchmarking results reported in the open literature raise optimistic expectations on use of optical networks-on-chip (ONoCs) for high-performance and low-power on-chip communication. However, most those previous works ultimately fail to make a compelling case chip-level nanophotonic NoCs, especially lack aggressive electronic baselines (ENoC), poor accuracy physical- architecture-layer analysis ONoC. This paper aims at providing guidelines minimum requirements so that emerging...

A decade after the beginning of many-core era, multi-core CPU and GPU architectures are everywhere, from mobile devices up to high-performance workstations servers. To this day, programmers willing harness their power need express code via languages frameworks that often lack expressivity high-level abstractions. These solutions, despite allowing users reach unprecedented performance, can still be a hampering factor for productivity portability. In paper we propose PHAST, modern C++,...

Elliptic-Curve cryptography (ECC) is promising for enabling information security in constrained embedded devices. In order to be efficient on a target architecture, ECCs require accurate choice/tuning of the algorithms that perform underlying mathematical operations. This paper contributes with cycle-level analysis dependencies ECC performance from interaction between features and actual architectural microarchitectural an ARM-based Intel XScale processor. Another contribution modified ARM...

Nanophotonic interconnection is a promising solution for inter-core communication in future chip multiprocessors (CMPs). Main benefits derive from its intrinsic low-latency and high-bandwidth, especially when employing wavelength division multiplexing (WDM), as well reduced power requirements compared to electronic NoCs. Existing works on optical NoCs (ONoC) mainly concentrate relatively complex proposals needed host the whole CMP traffic. In some complexity increased also need of an network...

gem5 is a popular architectural simulator, for both academic and industrial researchers. It can be used in two configurations: Full System mode Syscall Emulation mode. The former requires running real kernel to achieve realistic results, at the cost of increased user effort. In contrast, latter emulates operating system functionalities, which improves usability but more prone producing less accurate results. Due absence genuine mode, simulator model virtual address translation remains...

Abstract Different technologies and approaches exist to work around the performance portability problem. Companies academia together find a way preserve across heterogeneous hardware using unified language, one language rule them all. Intel's oneAPI appears with this idea in mind. In article, we try new Intel solution approach programming, choosing machine learning as our case study. More precisely, choose Caffe, framework that was created six years ago. Nevertheless, how would it be make...

This paper addresses feedback-directed restructuring techniques tuned to Non Uniform Cache Architectures (NUCA) in CMPs running multi-threaded applications. Access time NUCA caches depends on the location of referred block, so locality and cache mapping application influence overall performance. We show for altering distribution applications into space as achieve improved average memory access time. In applications, aggregated accesses (and locality) processors form actual load pose specific...

This paper proposes a tiled chip multiprocessor (CMP) architecture built around an all-optical reconfigurable network, thought to significantly reduce path-setup latency and energy consumption. We propose novel optical procedure that is able configure multiple switches simultaneously. Our uses simple ring-based network for assisting folded Torus Network-on-Chip (NoC) serving cache coherence traffic. investigate performance/power effects on CMP system we compare against both high-performance...

In this paper, we present an evaluation of possible ARM instruction set extension for elliptic curve cryptography (ECC) over binary finite fields GF(2/sup m/). The use is becoming common in embedded domain, where its reduced key size at a security level equivalent to standard public-key methods (such as RSA) allows power consumption savings and more efficient operation. processor was selected because it widely used system applications. We developed ECC benchmark with three algorithms:...

Fetching instructions from a set-associative cache in an embedded processor can consume large amount of energy due to the tag checks performed. Recent proposals address this issue involve predicting or memoizing correct way access. However, they also require significant hardware storage which negates much saving.

SUMMARY Nanophotonics promises to solve the scalability problems of current electrical interconnects thanks its low sensitivity distance in terms latency and energy consumption. Before this technology reaches maturity, hybrid photonic‐electronic networks will be a viable alternative. Ideally, ordinary meshes ring‐based photonic should cooperate minimize overall consumption, but currently, we lack mechanisms do efficiently. In paper, present novel fine‐grain policies manage resources tiled...

The continuous increase of the number cores in tiled chip-multi-processors (CMP) will prevent traditional electronic networks on chip (NoC) to maintain an acceptable tradeoff between performance and power consumption. Recent advances silicon-photonics open new opportunities for fast low-energy on-chip interconnections but specific design tuning is needed. This paper proposes Olympic, all-optical NoC architecture using a hierarchical topology made up replicated cascaded simple photonic...

Many crossbenchmarking results reported in the open literature raise optimistic expectations on use of optical networks-on-chip (ONoCs) for high-performance and low-power on-chip communication. However, most those previous works ultimately fail to make a compelling case chip-level nanophotonic NoCs, especially lack aggressive electronic baselines (ENoC), poor accuracy physical- architecture-layer analysis ONoC. This paper aims at providing guidelines minimum requirements so that emerging...

In the embedded domain, gap between memory and processor performance increase in application complexity need to be supported without wasting precious system resources: die size, power, etc. For these reasons, effective exploitation of small simple cache memories is utmost importance. However, programs running on such caches can experience serious inefficiencies due conflicts.We present a new Cache-Aware Code Allocation Technique (CAT), which transforms structure so that their behavior toward...

A multi-technology platform is considered to interact and cooperate with complex heterogeneous domestic or industrial environments. This way an automatic set up of the digital representation such spaces possible, that we shall call smart spaces, in which identifying, localizing, monitoring updating different real objects carried out time. Natural interaction tagged untagged items may then be by users' categories having various needs. accomplished augmenting RFID technology a) direction...

According to the ancient Romans, “Delectare, docere, movere” are goals of eloquence. To be accepted by museums, landscapes and archaeological sites, technology has win same challenge. Is unobtrusive enough avoid compromising emotional involvement that makes a visit cultural site unforgettable? Can it achieve dissemination information in such way is understood better? And how can used increase visibility understanding numerous sites not yet able attract amount people they deserve? This paper...

During the last years, hardware accelerators have been gaining popularity thanks to their ability achieve higher performance and efficiency than classic general-purpose solutions. They are fundamentally shaping current generations of Systems-on-Chip (SoCs), which becoming increasingly heterogeneous. However, despite diffusion, a standard, general solution manage them while providing speed consistency has not yet found. Common methodologies rely on OS mediation mix user-space kernel-space...