This paper introduces a new algorithm of extracting MFCC for speech recognition. The reduces the computation power by 53% compared to conventional algorithm. Simulation results indicate has recognition accuracy 92.93%. There is only 1.5% reduction in extraction algorithm, which an 94.43%. However, number logic gates required implement about half makes very efficient hardware implementation.

Deep neural networks (DNNs) have been widely applied in speech recognition and enhancement. In this paper we present some experiments using deep rectifier for denoising. Rectified linear units (ReLUs) can make a sparse connection between hidden layers. We analyze the usage of regularization coefficient during training to encourage more sparseness. This method further improves generalization ability DNN regression model unseen noisy conditions. After pruning retraining network, computation...

Closed-loop stimulation of many neurological disorders, such as epilepsy, is an emerging technology and regarded a promising alternative for surgical drug treatment. In this paper, real-time seizure detection algorithm based on STFT support vector machine (SVM) its field-programmable gate array (FPGA) implementation are proposed. With two-stage patient-specific channel selection feature mechanism, those redundant uncorrelated spectral features removed from the entire set. The evaluation...

This paper presents a new reversed nested Miller compensation technique for multistage operational amplifier (opamp) design. The inverts the sign of right half complex plane zero and shifts frequency conjugate poles to higher frequency. Simulation results indicate that gain-bandwidth product settling time are improved by factors two three, respectively, without degrading stability power consumption. To verify proposed technique, three-stage opamp is fabricated with 0.6-μm CMOS technology....

In this paper, an electrocardiographic (ECG) signal processing IC, which is used for portable biomedical application, was designed using continuous-time technique. The circuit consists of instrumentation amplifier (INA) with driven-right-leg (DRL), a 5th order G/sub m/-C low pass filter (G/sub LPF) operating in sub-threshold mode, and amplifiers. DRL to detect small amplitude the presence large common-mode voltage from human body. CMRR INA 78 dB LPF has cutoff frequency 18 Hz. As result DRL,...

A low-power, reliable and re-configurable clock recovery circuit for UHF RFID transponders the EPC Class-1 Generation-2 standard is proposed. Based on a digital frequency-locked loop, uses timing information available in downlink data, namely, pulse intervals of PIE-coded to calibrate an oscillator's output frequency meet stringent accuracy requirement standard. Fabricated 0.18-¿m CMOS technology, provides calibrated 2.56 MHz with deviation within range from -3.2% +1.2% over process, supply...

Correction of frequency-dependent I/Q mismatches in quadrature receivers The wideband designed for multi-channel reception can be and limit their image rejection performance to an unacceptable level. An adaptive signal-image separation system is proposed correct the digital domain. Simulation results verifying method are given.

Packet-switched networks on chip are emerging communication fabric to resolve the scalability and bandwidth limitation inherent in shared buses dedicated links. However current state-of-the-art on-chip network routers suffer from latency overhead. In this work, we propose a new router which makes use of dynamic lookahead bypass reduce latency. Special controlling pipeline is applied speed up allocation computations so that input buffers' bypassing rate increases. Lookahead bypasses not only...

As fabrication process technology continues to advance, mask set costs have become prohibitively expensive. Structured application specific integrated circuits (sASICs) offer a middle ground in price and performance between ASICs field-programmable gate arrays (FPGAs) by sharing masks across different designs. In this paper, two sASIC architectures are proposed, the first being based on three-input lookup-tables, second AOI22 gates. The sASICs programmed using standard-cell compatible design...

A novel digital frequency tuning technique is presented for integrated active RC filters. Instead of varying the values capacitors or resistors as in traditional approaches, proposed achieves by dividing currents that flow from to virtual grounds. Current division performed through a digitally programmable current network added at each ground. The features compact size, wide range and high linearity. Transistor level simulation results are demonstrate technique.

A passive UHF RFID tag's baseband processor design with energy-aware structure is presented in this paper, based on EPC C1G2 protocol. For the consideration of limited availability power and low-voltage supply, ripple-binary mixed counter compensated addition are proposed for PIE decoder. And clock generator tag-to-reader uplink, Galoi linear feedback shift register (LFSR) utilized to satisfy critical timing requirement. Additionally, double-edge-triggered (DET) flip flop these two modules...

This paper presents optimized synchronization algorithms and architecture designs of a downlink baseband receiver for multiband orthogonal frequency division multiplexing ultra wideband (MB-OFDM UWB). The system targets at low complexity power under the premise good performance. At algorithm level, dual-threshold (DT) detection method is proposed robust performance in timing synchronization; multipartite table (MTM) employed to implement arctangent sin/cos functions coarse synchronization....

Automated real time seizure detection is difficult since sensitivity, false rate and onset latency need to be considered simultaneously. Traditional pattern recognition classification system usually suffers huge performance variation due patient specificity algorithm inadaptability. To address this problem, we propose a two stage which integrates off-line channel selection feature before the construction of final model. This allows specific flexible set extraction for individual patient, so...

Brillouin optical time domain analyzer (BOTDA) fiber sensors have shown strong capability in static long haul distributed temperature/strain sensing. However, applications such as structural health monitoring and leakage detection, real-time measurement is quite necessary. The of a BOTDA system includes data acquisition post-processing time. In this article, we propose to use hardware accelerated support vector regression (SVR) for the collected data. Ideal Lorentzian curves under different...

Semicustom IC design methodologies often assume a wide range of operating conditions. This requirement makes designing output drivers very difficult, as ringing due to overdriving cannot be avoided. problem becomes more tricky when power noise simultaneous switching many at high speed is also considered. A new driver proposed that adopts an innovative feedback mechanism achieve adaptive characteristic so its performance will not vary under different loading The low in it works with principle...

In today's sub-micron CMOS integrated circuit technology, high speed output switching signals interacting with external inductance and capacitance produce noise which contaminates power buses. A Feedback Control Slew Rate Output Driver (FCSROD) reduces the spike down to approximately 64% of a conventional buffer without incurring penalty propagation delay even rise/fall time is described. This effective suppression achieved by using distributed weighted driver segments in conjunction...

This paper presents a design of analog Receiver Front End based on IntraBody Communication theory, which mainly concentrates the high data speed-2.5Mb/s and 5Mb/s, extremely long transmission distance-170cm, these specifications are seldom achieved in previous research but will play significant role be necessary further IBC applications. The ISI issue during body is also first discussed restrain this design. Furthermore, Return-to-Zero coding adopted to increase run length doesn't affect...

Many circuit modifications require only a slight adjustment to the IC layouts. General purpose placement algorithms cannot take advantage of these situations because they are designed generate complete from scratch. In this paper, we present two new effect incremental changes on gate array layout automatically. The will selectively relocate number logic elements vacate an empty slot. slot is then ready for added element. Results obtained prove that superior over simple-minded modification...

This paper presents a design procedure of high-frequency output driver with low power-bus noise and an architecture which automatically adapts to different loading. In depth analysis amplitude versus driving power as first stage is included the theoretical approach supported by simulation measurement results designed manufactured device.

This paper presents a 1.2 V 900 MHz CMOS mixer circuit using current mode multiplication. Besides the low voltage operation, new has very good linearity, and measured IIP/sub 3/ is equal to 10 dBm. The mixer-circuit specially designed for communication circuits RF CMOS. operating power consumption 3 mW.

Through low-level simulation and analysis, we find that the virtual channel allocator (VA) consumes large area power while it is not critical in performances of a NoC. Thus, possible to reduce costs VA with only small penalty network performances. This paper proposes two low-cost architectures: look-ahead unfair VA. Compared general VA, look- ahead reduces number both input VC arbiters output decreases size arbiters. Our experiments based on UMC 130 nm SP library show architectures jointly...

Remote control is already part of the everyday life. However, there no truly universal remote which can all appliances at home. This paper proposes an infra-red system make it a possibility. The based on innovative link procedure and demonstrated in controlling main switches. hardware software details are described. An ASIC chip for receiver designed to simplify integration with

Elliptic curve cryptography is becoming popular in recent decades due to its high security strength per bit, less memory resources and low processing power which makes it attractive for application energy constraint applications such as contact-less smart cards. In this paper, a 173-bit (m = 173) Type II Optimal Normal Basis (ONBII) representation chosen the implementation of Galois Field GF(2/sup m/) arithmetic logic unit by asynchronous architecture. This proposed architecture uses...