Taesik Cheung

ORCID: 0000-0003-4796-5726
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About
Contact & Profiles
Research Areas
  • Software-Defined Networks and 5G
  • Advancements in PLL and VCO Technologies
  • Radio Frequency Integrated Circuit Design
  • Advanced Optical Network Technologies
  • Interconnection Networks and Systems
  • Analog and Mixed-Signal Circuit Design
  • Network Traffic and Congestion Control
  • Advancements in Semiconductor Devices and Circuit Design
  • Network Time Synchronization Technologies
  • Semiconductor Lasers and Optical Devices
  • Smart Grid Security and Resilience
  • Semiconductor materials and devices
  • Low-power high-performance VLSI design
  • IPv6, Mobility, Handover, Networks, Security
  • Microwave Engineering and Waveguides
  • Network Security and Intrusion Detection
  • Photonic and Optical Devices
  • Optical Network Technologies
  • Advanced Power Amplifier Design
  • Network Packet Processing and Optimization
  • IoT and Edge/Fog Computing
  • Electromagnetic Compatibility and Noise Suppression
  • Innovation in Digital Healthcare Systems
  • Age of Information Optimization
  • Chaos control and synchronization

Electronics and Telecommunications Research Institute
2004-2024

University of Toronto
2003-2006

Delft University of Technology
2006

Micro Magnetics (United States)
2005

Yonsei University
1996-2003

The University of Tokyo
1996-2002

Fujitsu (Japan)
2002

This paper introduces floating shields for on-chip transmission lines, inductors, and transformers implemented in production silicon CMOS or BiCMOS technologies. The shield minimizes losses without requiring an explicit ground connection. Experimental measurements demonstrate Q-factor ranging from 25 to 35 between 15 40 GHz shielded coplanar waveguide fabricated on 10 /spl Omega//spl middot/cm silicon. is more than a factor of 2 improvement over conventional lines (e.g., microstrip, CPW). A...

10.1109/jssc.2006.872737 article EN IEEE Journal of Solid-State Circuits 2006-04-28

Transmission lines are implemented using an all-copper backend developed for RF and microwave applications. Wavelength reduction is used to achieve a Q factor >20 from 20GHz 40GHz, about three times higher than conventional transmission with the same technology. It has 0.3dB/mm loss, reduces wavelength of line by half thereby minimizing space on-chip devices.

10.1109/isscc.2003.1234353 article EN 2003-12-22

A three-stage 21-26-GHz medium-power amplifier fabricated in f/sub T/=120 GHz 0.2 /spl mu/m SiGe HBT technology has 19 dB small-signal gain and 15 at maximum output power. It delivers 23 dBm, 19.75% PAE 22 GHz, 21 13% 24 GHz. The differential common-base topology extends the supply to BV/sub CEO/ of transistors (1.8 V). New on-chip components, such as onchip interconnects with floating shields, self-shielding four-way power combining/dividing baluns provide inter-stage coupling single-ended...

10.1109/jssc.2005.857424 article EN IEEE Journal of Solid-State Circuits 2005-12-01

Differential shielding reduces substrate losses and improves the Q-factor of a monolithic inductor on silicon by up to 35% without process modification or patterned ground shield. Peak Qs 32 for 4 /spl mu/m thick aluminum 28 2.3 copper metals are demonstrated 10 Omega/-cm substrates 7.7 nH test inductor. The differential shield fulfills all existing metal density requirements, compact circuit model is presented that agrees within 8% measurement.

10.1109/cicc.2003.1249367 article EN 2004-01-24

The MPLS Transport Profile (MPLS-TP) is a framework for the construction and operation of reliable packet-switched transport networks based on architectures Pseudowires. Its development has been shared between IETF, where expertise resides, ITU-T, with its historic understanding networks. MPLS-TP adds two significant features to toolkit: Operations, Administration, Maintenance (OAM), linear protection switching. Unlike OAM, which resulted in application specific incompatible standards being...

10.1109/mcom.2014.6979981 article EN IEEE Communications Magazine 2014-12-01

Managing queuing delays is crucial for maintaining Quality of Service (QoS) in real-time media communications. Customizing traditional routing protocols to meet specific QoS requirements—particularly terms minimizing delay and jitter media—can be both complex time-intensive. Furthermore, these often encounter challenges when adapted vendor-specific hardware implementations. To address issues, this paper leverages the programmable features Software-Defined Networking (SDN) simplify process...

10.3390/app14199066 article EN cc-by Applied Sciences 2024-10-08

A monolithic 4-way power combining balun facilitates the implementation of 21 GHz to 27 amplifiers using silicon transistors. The combiner transforms a 50 /spl Omega/ output four 13 loads with 3% mismatch at 0.9 dB loss, novel symmetric, self-shielding design. This also enhances magnetic coupling coefficient (k>0.85) and reduces substrate loss skin effect mm-wave frequencies.

10.1109/cicc.2004.1358901 article EN 2004-11-30

Many circuit modifications require only a slight adjustment to the IC layouts. General purpose placement algorithms cannot take advantage of these situations because they are designed generate complete from scratch. In this paper, we present two new effect incremental changes on gate array layout automatically. The will selectively relocate number logic elements vacate an empty slot. slot is then ready for added element. Results obtained prove that superior over simple-minded modification...

10.1109/43.494707 article EN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1996-04-01

In this study, we propose a scalable framework that guarantees both latency and jitter bounds in large networks, including the Internet. The is composed of two parts: latency-guaranteeing network jitter-guaranteeing end system. For bounds, suggest regulators per class input–output port pair DiffServ-type relay nodes. based on guaranteed time-stamping buffers at egress edge. does not require network-wide time synchronization, frequency flow state maintenance, or flow-level queuing/scheduling....

10.1109/access.2022.3146398 article EN cc-by-nc-nd IEEE Access 2022-01-01

Shared mesh protection (SMP) is a mechanism that recovers traffic delivery against failures on working path as rapidly linear protection. In addition, it allows for resource sharing among the paths with different endpoints in network by coordinating use of shared resources when multiple compete these resources. Owing to limited and preemption consequence priority comparison, SMP introduces new optimization problem whose objective find optimal assignment maximizes number protected services...

10.1109/tcomm.2018.2884988 article EN IEEE Transactions on Communications 2018-12-05

A new charge pump structure is proposed that can improve jitter characteristics of a Phase-Locked Loop (PLL) by blocking the control voltage leakages. The also has low power consumption because it uses self-biased method switches current flow only on demand. PLL with designed 0.6 /spl mu/m CMOS process technology and evaluated post-layout simulation.

10.1109/icvc.1999.821010 article EN 2003-01-20

We consider guaranteeing end-to-end (E2E) latency bounds to flows in a network. It is desirable that are isolated from other flows. The bursts or the network utilization level should not affect flow’s bound. fair queuing technique, which includes Packetized Generalized Processor Sharing (PGPS) and Virtual Clock (VC), based on concept of ideal packet service completion time called Finish Time (FT). known provide best flow isolation but suffers fact it has maintain states. Alternative schemes...

10.1109/access.2023.3318479 article EN cc-by-nc-nd IEEE Access 2023-01-01

Many precautions are taken to avoid damaging electrostatic discharge (ESD) through disk drive magnetic recording heads featuring readback via a magnetoresistive (MR) sensor. By optimizing protective spark-gaps (PSG) in the head, extent of ESD damage can be reduced. Human Body Model (HBM), Machine (MM) and Charged Device (CDM) transients applied simulated soft-adjacent-layer (SAL)-biased MR with without spark-gaps. Design principles for ESD-damage-suppressing developed several implementations...

10.1109/eosesd.1996.865119 article EN 2005-08-24

In this paper, we discuss the issues of supporting protection switching in multiple recovery domains (MRDs). MRDs, dual node interconnection (DNI) between two adjacent is essential to provide reliable services for customers whose traffic traverses domains. Existing linear solutions packet transport networks, such as multiprotocol label switching-transport profile (MPLS-TP) and Ethernet, support an end-to-end flow end nodes a domain; however, they do not DNI capability We propose scheme with...

10.1109/jlt.2018.2820144 article EN Journal of Lightwave Technology 2018-03-28

This paper introduces the fully centralized control plane of DetNet that was based on OpenDaylight SDN controller developed, and this plane, a remote test 5G industrial loT-based smart factory demonstrated.

10.1109/ictc55196.2022.9952966 article EN 2022 13th International Conference on Information and Communication Technology Convergence (ICTC) 2022-10-19

Packet losses in the network significantly impact performance. Most TCP variants reduce transmission rate when detecting packet losses, assuming congestion, resulting lower throughput and affecting bandwidth-intensive applications like immersive applications. However, not all are due to congestion; some occur wireless link issues, which we refer as non-congestive losses. In today's hybrid Internet, packets of a single flow may traverse wired segments reach their destination. should react...

10.48550/arxiv.2408.03007 preprint EN arXiv (Cornell University) 2024-08-06

10.1109/ictc62082.2024.10827784 article EN 2022 13th International Conference on Information and Communication Technology Convergence (ICTC) 2024-10-16

This work investigates how hierarchical quality of service (QoS) could be realized in PBB-TE networks. The QoS mechanism is implemented using two rate three color marker (trTCM) and weighted fair queuing (WFQ) algorithms. We verify the performance by measuring policing accuracies for four levels.

10.1109/coin.2010.5546692 article EN 2010-07-01

Two new phase/frequency detectors (PFDs) are proposed that can overcome the speed and jitter limitations of conventional PFD schemes. One circuits has a reset time 0.32 ns other 0.03 during phase-locked loop capture process, according to HSPICE simulation with 0.8 µm CMOS process parameters.

10.1049/el:19981493 article EN Electronics Letters 1998-10-29

A chip-to-chip signaling scheme employs partial response detection (PRD) combined with the zero-delay time delivery of a global timing reference, or mean (GMT). High-output-impedance drivers and higher termination resistances for signal transmission reduce driver power to 10 mW range while maintaining data rate 500Mb/s. The resulting intersymbol interference (ISI) is eliminated by PRD receivers, type auto-zero-comparator. Signal lines are segmented pipelined buffers limit segment lengths...

10.1109/isscc.1998.672418 article EN 2002-11-27

The ultra-low latency service provides very short network delays and can implement Internet services at the level of tactile interaction. However, in order to provide end-to-end over a long distance, infrastructure needs support DetNet services. Therefore, this paper reliable with limited low jitter such as an service, thereby providing stable connection improved resource efficiency. In addition, aims active control management system that quickly adjust resources according predicted conditions events

10.1109/icufn49451.2021.9528759 article EN 2021-08-17
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