Previous works on transistor reliability are mostly devoted to ON-state degradations, such as bias temperature instability and hot carrier degradation, for which physical models have been developed describe corresponding mechanisms. However, very limited data OFF-state degradation is available, especially in FinFET technology. In the first part of this article, OFF-sate degradations 7-nm technology reported time. The physics mechanisms proposed by combining TCAD simulations comprehensive...

Due to severer transistor aging at nanoscale, circuit design margin becomes extremely tight for advanced technology nodes. Thus, reliability-aware is urgently needed. In this article, a new framework perform aging-aware static timing analysis (STA) presented reliability analysis. The key parts of STA flows are workload and aged delay/transition calculation. For the analysis, analytical stress probability (SP) calculation model proposed, which considers floating effect signal correlations....

With transistor scaling to nanometer region, aging effects become a non-neglectable issue in circuit design. Aging-aware standard cell library is necessary for robust To consider libraries, existing methods mostly require simulating all combinations of variables and timing arcs, which are unscalable large cells. In this brief, we propose an efficient aging-aware characterization framework based on sensitivity analysis. We introduce the concept critical transistors, can be extracted by By...

Stochastic computing (SC) presents high error tolerance and low hardware cost, has great potential in applications such as neural networks image processing. However, the bitstream generator, which converts a binary number to bitstreams, occupies large area energy consumption, thus weakening superiority of SC. In this paper, we propose novel technique for generating bitstreams parallel, needs only one clock conversion significantly reduces cost. Synthesis results demonstrate that proposed...

Part I of this article revealed that the OFF-state degradation consists both bias temperature instability (BTI) and hot carrier (HCD) traps in different channel regions. In part II article, a compact aging model advanced FinFETs is developed validated by silicon data 7-nm node, including recovery phases. The capable to cover various types devices, such as n/p types, core/IO with short/long-channels. Meanwhile, trap contributions over time are discussed based on component analysis....

The self-heating effect (SHE) is a critical issue in nanoscale fin field transistors (FinFETs) that has emerged as an essential concern for device reliability. In physical circuit operations, devices generally suffer from mixed-mode hot carrier degradation (HCD) and bias temperature instability (BTI) stress conditions. transient SHE at the HCD stage affects BTI, resulting inadequacy of existing aging models. this article, we develop accurate model incorporate it into HCD-BTI reliability...

Reliability-enhanced circuit design is increasingly demanded due to severer transistor aging and variations at nanoscale. In this brief, new insights of inherently enhancing reliability are presented, based on the emerging computing paradigm stochastic (SC). A cross-layer simulation flow supporting statistical static timing analysis (SSTA) proposed, with a long-term compact model validated by 16/14nm FinFET experimental data. Then, SC circuits in practical applications investigated compared...

After the completion of multi-stage fracturing operation, fluid pressure in artificial fracture network continues to decrease, resulting closure and variation local induced stress field. This process can also lead propagation pattern subsequent stages. To better guide design, time effect field was researched. A numerical method used solve around a propped fracture, analyze influence formation properties treatment parameters on its change. Then, characteristics with different times were...

In this paper, random telegraph noise (RTN) in advanced multi-Fin bulk FinFETs are comprehensively studied for the first time. Based on statistical experiments, complete categories of simple and complex RTNs identified analyzed details. Especially, anomalous "reversal RTN" induced by 2 metastable states single oxide trap, found not rare, but appears at a certain percentage, which provides unique opportunity statistically studying directly from RTN measurements. addition, layout dependence...

Convolutional neural network (CNN) achieves excellent performance on fascinating tasks such as image recognition and natural language processing at the cost of high power consumption. Stochastic computing (SC) is an attractive paradigm implemented in low applications which performs arithmetic operations with simple logic hardware cost. However, conventional memory structure designed optimized for binary leads to extra data conversion costs, significantly decreases energy efficiency....

With the downscaling of CMOS technology, circuit design margin becomes more and tight due to wider guardband, which is required counteract severer transistor aging variations. Thus, reliability-enhanced urgently needed reduce guardband. In this paper, a framework based on approximate synthesis proposed completely eliminate It mainly includes two key parts: first, forward reliability simulation flow supporting statistical static timing analysis (SSTA) performed estimate path failure rates...

As the transistor shrinks to nanoscale, overhead of ensuring circuit functionality becomes extremely large due increasing timing variations. Thus, better-than-worst-case design (BTWC) has attracted more and attention. Many these techniques utilize dynamic slack (DTS) activity information for optimization runtime tuning. Existing DTS computation methods are essentially a modification worst-case delay information, which cannot guarantee exact simulation, causing performance degradation in...

Previous energy-efficient neural network (NN) processors suffer from bit errors when operating at lower voltages for further power reduction. Stochastic computing (SC) shows great potential due to its low hardware cost and high fault tolerance. Conventionally, limited by the long latency of bitstreams, SC-based NN accelerators adopt a hybrid stochasticbinary architecture, sacrificing tolerance efficiency. This paper proposes fully SC architecture that maximizes while offering excellent...

As the timing guardband continues to increase with continuous technology scaling, better-than-worst-case (BTWC) design has gained more and attention. BTWC can improve energy efficiency and/or performance by relaxing conservative static constraints exploiting dynamic margin. However, avoid potential reliability hazards, existing analysis (DTA) tools have add extra aging variation guardbands, which are estimated under worst-case corners of variation. Such guardbanding method introduces...

As the timing guardband consumes more and design margin with technology scaling, better-than-worst-case (BTWC) techniques have gained attention as a promising solution. BTWC can relax by transcending pessimistic static constraints utilizing dynamic information. However, to guarantee reliability throughout lifetime, conventional analysis (DTA) engines need an extra guardband, which is commonly evaluated under worst-case corners of aging variation. This type guardbanding precious margin, thus...

Platform well fracturing is essential for the efficient development of unconventional oil and gas (UOG), it has been widely applied in oilfields. Field practices have revealed that various methods result different stimulation performances, but mechanisms responsible these differences are not completely understood. To explore characteristics inter-well stress interference platform methods, a numerical model was established systematic assessment field simultaneous fracturing, zipper (ZF),...

The following topics are dealt with: CMOS integrated circuits; MOSFET; low-power electronics; elemental semiconductors; silicon; circuit design; analogue-digital conversion; III-V field programmable gate arrays; technology CAD (electronics).

With CMOS technology shrinking into nanoscale, the circuit design margin has become extremely tight due to severer transistor aging and process variations. To relieve reliability problems, many optimization methods have been proposed. In essence, all these trade off area/power /performance for reliability. this paper, we present a new perspective enhance reliability: using emerging computing paradigms. As preliminary attempts, three reliability-enhanced flows based on approximate and/or...

In this work, a novel Spin Torque Nano Oscillator (STNO) device which can sustain high frequency oscillation without demand of bias magnetic field is proposed. Voltage Controlled Magnetic Anisotropy (VCMA) effect employed to increase perpendicular anisotropy leading in the absence field. addition, VCMA also be utilized as modulation approach realize signal for STNO used communication system.

Convolutional neural networks (CNN) have achieved excellent performance on various tasks, but deploying CNN to edge is constrained by the high energy consumption of convolution operation. Stochastic computing (SC) an attractive paradigm which performs arithmetic operations with simple logic gates and low hardware cost. This paper presents energy-efficient mixed-signal multiply-accumulate (MAC) engine based SC. A parallel architecture adopted in this work solve latency problem The simulation...

Design for reliability (DFR) in advanced technology nodes has become an increasingly challenging task, which requires comprehensive support from aging-aware EDA tools and optimization design flows. In this paper, our recent studies on the cross-layer are summarized, especially perspectives. The advances modeling device-level, a set of analysis frameworks at circuit level system overviewed. results demonstrate that DFR framework enables accurate to reduce over-design optimize PPA across...

Deep neural networks (DNNs) have revolutionized different applications ranging from computer vision to natural language processing, and are widely deployed in data centers edge devices. It can be foreseen that DNNs will applied more safety-critical like autonomous driving robotics, which typically require highly reliable computing avoid catastrophic consequences. Therefore, not only the model's robustness against various perturbations adversarial noise, but also of silicon-based accelerators...

With the rapid advancements of deep learning in recent years, hardware accelerators are continuously deployed more and safety-critical applications such as autonomous driving robotics. While usually fabricated with advanced technology nodes for high performance energy efficiency, they also prone to timing errors under process, voltage, temperature, aging (PVTA) variations. By revisiting physical sources errors, we show that most accelerator caused by a specific subset input patterns, defined...