This article presents an energy-efficient comparator design. The pre-amplifier adopts inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting gm/ID reducing noise. Moreover, greatly reduces the influence of process corner common-mode voltage on performance, including noise, offset, delay. A prototype in 180 nm achieves 46-μV input-referred noise while consuming only 1 pJ per comparison under 1.2-V...

This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed amplifier combines the merits of architecture operation, realizing robustness, high accuracy, energy-efficiency simultaneously. It is embedded in loop filter an NS SAR design, enabling first fully NS-SAR ADC that realizes sharp noise transfer function (NTF) while not...

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this provides a comprehensive survey of state-of-the-art techniques every circuit block in SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), logic. The goal is to provide useful ADC designers who want improve energy efficiency targeting low-to-medium...

This paper presents a power-efficient noise reduction technique for successive approximation register analog-to-digital converters (ADCs) based on the statistical estimation theory. It suppresses both comparator and quantization error by accurately estimating ADC conversion residue. allows high signal-to-noise ratio (SNR) to be achieved with noisy low-power relatively low resolution digital-to-analog converter (DAC). The proposed has hardware complexity, requiring no change standard...

Due to sensitive layout-dependent effects and varied performance metrics, analog routing automation for performance-driven layout synthesis is difficult generalize. Existing research has proposed a number of heuristic constraints targeting specific metrics. However, previous frameworks fail automatically combine with human intelligence. This paper proposes novel, fully automated, paradigm that leverages machine learning provide guidance, mimicking the sophisticated manual approaches....

Noise-shaping (NS) SAR ADCs using passive loop filters have drawn increasing attention due to their simplicity, low power, zero static current, and PVT robustness. However, prior works show limited resolution (ENOB≤13b) two main challenges. The 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> one is thermal noise. Passive cannot provide gain [1]. Hence, suppression of the comparator noise limited. In addition, every capacitor switching...

Many applications, such as multi-standard wireless and event-driven IoT devices, demand high-resolution ADCs with scalable sampling rate power consumption. The conventional pipelined ADC can achieve high resolution, but its does not scale well the due to use of a closed-loop static OTA for residue amplification. While be turned off save power, it requires considerable time bias circuit CMFB loop settle when waking up, leading wasted reduced peak operation frequency. Using an open-loop...

In-Memory Computing (IMC), which takes advantage of analog multiplication-accumulation (MAC) insides memory, is promising to alleviate the Von-Neumann bottleneck and improve energy efficiency deep neural networks (DNNs). Since time-domain (TD) computing also an energy-efficient paradigm, we present 8kb mixed-signal IMC macro, TD-SRAM, by combining with TD computing. A dual-edge single input (DESI) topology proposed, can significantly area power efficiencies cell. The TD-SRAM bitcell...

This article presents a compact, robust, and transposable SRAM in-memory computing (IMC) macro to support feed forward (FF) back propagation (BP) computation within single macro. The transpose is created with clustering structure, eight 6T bitcells are shared one charge-domain unit (CCU) efficiently deploy the DNNs weights. normalized area overhead of structure compared cell only 0.37. During computation, CCU performs robust operations on parasitic capacitances local bitlines in IMC cluster....

Despite tremendous advancement of digital IC design automation tools over the last few decades, analog layout is still heavily manual which very tedious and error-prone. This paper will first review history, challenges, current status automation. Then, we present MAGICAL, a human-intelligence inspired, fully-automated system currently being developed under DARPA IDEA program. It starts from an unannotated netlist, performs automatic constraint extraction device generation, then placement...

This paper presents a time-interleaved (TI) SAR analog-to-digital converter (ADC) with fast variance-based timing-skew calibration technique. It uses single-comparator-based window detector (WD) to calibrate the timing skew. The WD can suppress variance estimation errors and allow precise from significantly small number of samples. has low-hardware cost orders magnitude faster convergence speed compared prior proposed technique brings collateral benefit offset mismatch calibration. After...

This article presents a capacitively coupled voltage-controlled oscillator (VCO)-based sensor readout featuring hybrid phase-locked loop (PLL)-ΔΣ modulator structure. It leverages phase-locking and phase-frequency detector (PFD) array to concurrently perform quantization dynamic element matching (DEM), much-reducing hardware/power compared with the existing VCO-based readouts' counting scheme. A low-cost in-cell data-weighted averaging (DWA) scheme is presented enable highly linear tri-level...

Noise shaping (NS) SAR ADCs combine the merits of and Δσ ADCs, can simultaneously achieve high power efficiency resolution. The key operation in an NS is residue integration. One way to implement it use a conventional closed-loop OTA [1]-[2]. It robust against PVT variation realize sharp noise transfer function (NTF), but consumes static does not scale easily. Another passive filter [3]-[4]. consume any current, its NTF less aggressive. Moreover, because gain low, suppression comparator...

In back-end analog/mixed-signal (AMS) design flow, well generation persists as a fundamental challenge for layout compactness, routing complexity, circuit performance and robustness. The immaturity of AMS automation tools comes to large extent from the difficulty in comprehending incorporating designer expertise. To mimic behavior experienced designers generation, we propose generative adversarial network (GAN) guided framework with post-refinement stage leveraging previous high-quality...

As any analog-to-digital converter (ADC) with a front-end sample-and-hold (S/H) circuit, successive approximation register (SAR) ADC suffers from fundamental signal-to-noise ratio (SNR) challenge: its sampling kT/C noise. To satisfy the SNR requirement, input capacitor size has to be sufficiently large, leading great burden for design of driver and reference buffer. This article presents an SAR noise-cancellation technique. It enables substantial reduction but without large noise penalty....

This article presents MAGICAL, which is a fully automated analog IC layout system. MAGICAL takes netlist and design rules as inputs, it produces the final GDS in fashion.

The Noise-Shaping (NS) SAR is an attractive new ADC architecture that emerged in the last decade. It combines advantages of and DSM architectures. NS shows excellent potential for high efficiency low cost, highly suited to process scaling. This paper gives overview history NS-SAR, reviews fundamentals challenges, summarizes latest developments, including advanced loop filtering techniques, DAC mismatch mitigation, kT/C bandwidth boosting. A comprehensive comparison state-of-the-art NS-SAR...

Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness. However, prior works show limited resolution because of two main challenges: thermal noise digital-to-analog converter (DAC) mismatch. This article presents a high-resolution full NS SAR ADC. It uses an efficient filter architecture that realizes 4...

The noise-shaping (NS) SAR is an emerging hybrid architecture that aims to combine the benefits of both and ΔΣ ADCs [1-8]. key in NS filter. As shown Fig. 27.1.1, prior filter techniques can be classified into two types. first way use a closed-loop amplifier-based integrator [1-3]. With sufficient gain amplifier, this type realize sharp noise transfer function (NTF). However, high-gain multi-stage amplifier produces large noise, power-consuming unfriendly technology scaling [2,3]. second...

To design noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs) with high resolution and good power efficiency, two key bottlenecks need to be addressed. One is realize a high-order loop filter low circuit overhead, the other mitigate thermal noise. This article presents an NS-SAR ADC that synergistically addresses both challenges. achieve it proposes innovative error feedback-cascaded integrator feedforward (EF-CIFF) structure realizes third-order...

Pipelined ADCs are widely used for high-speed high-resolution applications, but there two challenges. First, limited by the kT/C noise requirement, its 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -stage sampling capacitor has to be sufficiently large (e.g., several pF). This poses significant burdens ADC driver and reference buffer, leading high design complexity huge power/area costs on system level, especially when linearity,...

With the rapid advancement of edge AI, complexity tasks on devices is continually increasing, demanding better efficiency and precision from AI accelerators. Pre-aligned floating-point computing-in-memory (FP CIM) has been proposed to achieve high-precision neural network (NN) computations based (FP) data precision. However, complex digital circuitry required for integer (INT) mantissa multiply-accumulate (MAC) computation exponent alignment severely limits throughput FP CIM. This work...