A5052301198- Analog and Mixed-Signal Circuit Design
- CCD and CMOS Imaging Sensors
- Advancements in Semiconductor Devices and Circuit Design
- Advancements in PLL and VCO Technologies
- Low-power high-performance VLSI design
- Particle Detector Development and Performance
- Energy Harvesting in Wireless Networks
- Radio Frequency Integrated Circuit Design
- Innovative Energy Harvesting Technologies
- Radiation Effects in Electronics
- Advanced Combustion Engine Technologies
- Advanced Control Systems Optimization
- Advanced Sensor and Energy Harvesting Materials
- Analytical Chemistry and Sensors
- Combustion and flame dynamics
- VLSI and Analog Circuit Testing
The University of Texas at Austin
2019-2022
Analog Devices (United States)
2021
Tsinghua University
2018
National Taiwan University
2015
Industrial Technology Research Institute
2008-2012
This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed amplifier combines the merits of architecture operation, realizing robustness, high accuracy, energy-efficiency simultaneously. It is embedded in loop filter an NS SAR design, enabling first fully NS-SAR ADC that realizes sharp noise transfer function (NTF) while not...
Noise shaping (NS) SAR ADCs combine the merits of and Δσ ADCs, can simultaneously achieve high power efficiency resolution. The key operation in an NS is residue integration. One way to implement it use a conventional closed-loop OTA [1]-[2]. It robust against PVT variation realize sharp noise transfer function (NTF), but consumes static does not scale easily. Another passive filter [3]-[4]. consume any current, its NTF less aggressive. Moreover, because gain low, suppression comparator...
Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness. However, prior works show limited resolution because of two main challenges: thermal noise digital-to-analog converter (DAC) mismatch. This article presents a high-resolution full NS SAR ADC. It uses an efficient filter architecture that realizes 4...
Device mismatch is a key concern for high-resolution data converters. This paper presents comprehensive study of the error-feedback (EF)-based error shaping (MES) technique. EF MES overcomes challenge classic dynamic element matching-based whose complexity grows exponentially with number bits; however, prior comes limitations limited capability and reduced range. demonstrates how to perform more advanced various types Moreover, this also proposes use digital prediction address range loss issue.
This article presents an enhanced interstage gain error shaping (GES) technique that adopts a digital feedback (DEF) method to address the truncation in prior implementation, which can extend tolerance by five times. The proposed DEF does not introduce additional errors as it operates purely domain. also proposes first-order passive quantization noise (NS) reduces input-pair ratio of two-input-pair comparator 2.7 times, thus alleviating penalty caused using multiple-input-pair comparator. A...
This article presents an interstage gain error shaping (GES) technique that can substantially suppress the in-band quantization leakage caused by in pipeline analog-to-digital converters (ADCs). It works for both closed-loop and open-loop amplification. does not require extra clock phases, long convergence time or interruption of digitization, incur large power area overhead, pose a constraint on input signal. A prototype ADC equipped with proposed second-order GES 40-nm CMOS achieves...
This work introduces a second-order voltage-controlled oscillator (VCO)-based continuous-time delta-sigma modulator (CTDSM) that incorporates distributed-input VCO as the second-stage integrator and quantizer. The topology virtually eliminates VCO's voltage-to-frequency (V-F) parasitic pole. One of key ideas this article is to demonstrate use capacitive-π network in modulator's loop filter break constraint between size inner capacitive digital-to-analog converter (DAC) factor by which...
The kT/C noise poses a fundamental SNR limit for discrete-time (DT) ADCs with front-end sampling operations. To achieve high resolution, the capacitor needs to be sufficiently large (e.g., 3pF 80dB assuming 2V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> swing) and it has quadrupled every 1b increase in resolution. A critical challenges both ADC input buffer reference (Fig. 3.4.1). meet stringent linearity requirement of...
A 10-b pipeline ADC employing a coarse and fine stage in the 4.5-b front-end is proposed to achieve low power 90-nm CMOS technology. The highly relaxes linearity requirement of op amp complexity comparators. Hence, only very low-gain amplifier needed for interstage residue amplification without increasing comparator design. Operating at 400-MS/s sampling rate, consumes 8.7 mW from 1-V supply. It achieves signal-to-noise-plus-distortion (SNDR) better than 55 dB over entire Nyquist band.
This paper presents a low-cost gain error shaping (GES) technique that can substantially suppress the in-band interstage in pipeline ADCs. It works for both closed-loop and open-loop amplification. A prototype ADC with proposed 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order GES 40nm CMOS achieves 75.8dB SNDR over 12.5MHz BW while operating at 100MS/s consuming 1.54mW. 174.9dB Schreier FoM. The GES-related hardware occupies...
This paper presents an enhanced interstage gain error shaping technique that adopts a digital feedback to extend the tolerance by 5 times. also proposes passive quantization reduces ratio of two-input-pair comparator 2.7 A prototype equipped with proposed techniques is implemented in 40nm CMOS. It achieves SNDR 77.1 dB over 6.25-MHz bandwidth while operating at 100 MS/s and consuming 1.38 mW. 173.7 Schreier FoM.
The focus of this article is to characterize the behavior metal-oxide-metal (MOM) capacitors when used in a switched-capacitor circuit standard 65-nm 1.2-V CMOS technology subject ionizing radiation. goal twofold: first, understand radiation-induced single-event effects on fundamental building block analog circuits unconstrained by particular application and second, explore capacitor's use as particle detector analogous diode active-pixel sensor. signal response from MOM capacitor structures...
This letter analyzes the constraints and tradeoffs involved in design of a third-order single-bit quantizer-based continuous-time delta–sigma modulator (CTDSM) with hybrid active–passive loop filter. The jitter suppression capability an FIR DAC is combined superior out-of-band quantization noise filtering passive filter, thereby enabling use energy-efficient Gm-C integrator at front-end. Nearly 60 percent dc gain derived from quantizer, thus greatly relaxing requirement for active...
The stringent radiation-tolerance, quantization requirements, and the need for seamless integration of on-detector readout electronics chain require design a full-custom analog-to-digital converter (ADC) 182,468 channels in ATLAS Liquid Argon (LAr) calorimeter at Large Hadron Collider (LHC) CERN, as part High-Luminosity LHC (HL-LHC) upgrade. Each 8 prototype 65 nm CMOS ADC with 15-bit resolution >68 dB signal-to-noise-and-distortion ratio (SNDR), or equivalently >11 effective number bits...
Over the past years, there are growing interests on scavenging energy from ambience for portable and low-power electronic devices. Among these devices, wireless sensor networks combined with piezoelectric power harvesting devices most promising scenario which using cantilever beam structure excited by ambient vibrations to convert mechanical vibration electric sensors. It is known that environmental excitation frequency will not be always same as resonant of beam. However, under have highest...