A5026277721- Advancements in PLL and VCO Technologies
- Analog and Mixed-Signal Circuit Design
- Photonic and Optical Devices
- Semiconductor Lasers and Optical Devices
- VLSI and Analog Circuit Testing
- Radio Frequency Integrated Circuit Design
- CCD and CMOS Imaging Sensors
- Advancements in Semiconductor Devices and Circuit Design
- Optical Network Technologies
- Evolutionary Algorithms and Applications
- Blind Source Separation Techniques
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Electromagnetic Compatibility and Noise Suppression
Huawei Technologies (Canada)
2017-2019
University of Toronto
2010-2018
University of Cambridge
2015
Western Digital (United States)
1989
This paper presents a referenceless baud-rate clock and data recovery (CDR) incorporated with continuous-time linear equalizer (CTLE) one-tap decision feedback (DFE) to achieve rates from 22.5 32 Gb/s across channel Nyquist loss ranging 10.1 14.8 dB. The CDR includes proposed frequency acquisition scheme that consists of two parts: detection correction. Frequency is achieved by examining rising falling waveforms detect discrepancies between the rate locally recovered frequency. correction...
A loop gain adaptation technique is proposed, which optimizes the jitter tolerance (JTOL) of a 28 Gb/s phase interpolator (PI)-based clock and data recovery (CDR) circuit implemented in nm CMOS. The increases CDR's to suppress most while monitoring autocorrelation function bang-bang detector (BB-PD) output prevent CDR from becoming too underdamped. proposed requires no knowledge latency or input characteristics.
Analog mixed-signal (AMS) receivers for 50+Gb/s PAM-4 offer lower power than ADC-DSP [1]-[3]. Those using DFEs [2]-[3] suffer from relatively high consumption due to the large number of latches needed in speculative DFEs. Better efficiency can be achieved only a CTLE [1]. However, analog front-ends (AFEs) are sensitive variations process, supply voltage and temperature. To combat this while accommodating links with loss exceeding 20dB, an AFE extensive programmability is combined efficient...
A 15-bit low-power incremental ADC is designed for sensor applications. The to be frequency-scalable by 1000 times from 1.67S/s 1.67kS/s. To reduce power, an opamp with class AB characteristics used. design was fabricated in 0.18/μm CMOS and occupies area of 0.35mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Configured operate at full-rate as a Delta-Sigma modulator, the achieves 91.8dB peak SNDR while consuming 83μW 1.8-V supply....
This paper proposes a 10-Gb/s blind baud-rate ADC-based CDR. The operation is made possible by using 2UI integrate-and-dump filter, which creates intentional ISI in adjacent bit periods. samples are interpolated to recover center-of-the-eye for speculative Mueller–Muller PD and 2-tap DFE operation. A test chip, fabricated 65-nm CMOS, implements CDR with measured high-frequency jitter tolerance of 0.19 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML"...
As we move to higher data rates, the performance of clock and recovery (CDR) circuits becomes increasingly important in maintaining low bit error rates (BER) wireline links. Digital CDRs are popular part for their robustness, but use bang-bang phase detectors (BB-PD) makes sensitive changes jitter caused by PVT variations, crosstalk or power supply noise. This is because gain a BB-PD depends on CDR input jitter, causing loop change if magnitude spectrum varies. problem illustrated Fig. 6.7.1...
Baud-rate clock and data recovery circuits (CDRs) are becoming more prevalent in high-speed receiver designs as they offer lower power consumption by sampling the received only once per UI [1,2]. This reduces number of front-end comparators distribution networks [1]. However, current baud-rate CDRs require an external reference [1,2], adding to system complexity pin count generation. While frequency detectors (FDs) allow CDR operate without a across wide capture range [3-5], FDs not designed...
On-chip jitter measurement can be used to optimize the performance of wireline transceivers. In this work, random data is measured on-chip by correlating phase detector outputs from two adjacent CDR lanes. This allows jitter's autocorrelation function estimated, which RMS value and power spectral density are extracted without using any external reference clock. The ranging 0.85 ps 1.89 ps, sinusoidal 0.89 5.1 in PRBS31 with less than 0.6 error compared measurements an 80 GS/s real-time...
We present a technique to measure random jitter in phase interpolator (PI)-based clock and data recovery (CDR) circuit by injecting controlled amount of square-wave into its edge monitoring effect on the autocorrelation function CDR's bang-bang detector output. Jitter is injected adjusting code PI while measured on-chip counters. Since only affects clock, CDR remains operational during injection. Using this technique, rms relative between at input can be estimated with sub-picosecond...
ADC-based receivers process the received data in digital domain, eliminating need for much of analog front end. In addition, a feed-forward blind architecture [1,2] eliminates feedback loop between and domains so that ADC CDR can be designed simulated independently. Previous works sampled incoming at 2 samples per UI 1.45 to achieve 5Gb/s 6.875Gb/s, respectively. To further increase rate 10Gb/s, we sample baud (1 UI). Existing baud-rate architectures [3] rely on phase-tracking clock middle...
This letter presents a 56.25-Gb/s analog-mixed signal pulse amplitude modulation (PAM)-4 receiver in 7-nm fin field effect transistor (FinFET) CMOS. The uses an analog front-end (AFE) with extensive programmability and can equalize channels up to 22.3-dB loss at 14 GHz. AFE settings are optimized using genetic adaptation algorithm find the global minima for bit-error-rate (BER). A PAM-4 clock recovery scheme is proposed that reduces number of required edge samplers bang-bang phase detector...
We propose a technique to estimate the relative jitter between input data and recovered clock of 28Gb/s half-rate digital PI-based CDR without using an eye monitor. Instead, we inject square wave with known amplitude into CDR, by adding corresponding signal CDR's PI code. By measuring effect injected on autocorrelation function bang-bang PD output, RMS is estimated sub-picosecond accuracy, as demonstrated test chip fabricated in 28nm CMOS.
This paper proposes using a 3-bit ADC to blindly sample the received data from channel with 20 dB loss at Nyquist 3× baud rate. By moving 2× sampling, we reduce required resolution 5-bit 3-bit, thereby reducing overall power consumption by factor of 2. Measurements our test chip fabricated in Fujitsu's 65 nm CMOS show high frequency jitter tolerance 0.25 UIpp for 5 Gb/s PRBS31 60" FR4 channel.
A secondary communication link, or side-channel, is proposed, which uses binary frequency shift keying to modulate the of a high-speed wireline transmitter clock. This side-channel data then received using corresponding receiver's conventional clock and recovery (CDR) circuit. An analysis CDR loop parameters demonstrates that, within certain limits, does not impact signal integrity primary data. Measurements were made on prototype 56-Gb/s PAM-4 (half-rate 14-GHz clock) transceiver in 7-nm...
The design of a 4× blind analogue‐to‐digital converter (ADC)‐based receiver implemented in 65 nm CMOS technology is presented. ADC, which has three levels with two adjustable thresholds, effectively implements speculative decision‐feedback equaliser. By reducing the ADC resolution and by simplifying digital clock data recovery design, power consumption reduced factor 2 compared previous works. Measurement results confirm bit error rate <10 − 12 at 5 Gbit/s high‐frequency jitter tolerance...
On-chip jitter measurement is demonstrated in a 10Gb/s CDR by correlating the phase detector outputs of two adjacent lanes. The RMS received data and an estimate jitter's power spectral density are then extracted without using external reference clock. Circuits implemented 65nm CMOS measure random ranging from 0.85ps to 1.89ps PRBS31 with no more than 100fs error compared 80GS/s real-time oscilloscope. Sinusoidal 0.89ps 5.1ps measured worst-case 580fS
A differential phase-locked-loop architecture that can be used in high-speed data recovery systems is described. The has superior tracking performance the presence of noise and thus bit-error-rate compared to conventional single-ended realization. For operation at 10 Mb/s using a Manchester line code, theoretical limit ±25-ns jitter margin been approached. device, which fabricated 1.25-μm digital CMOS process, includes zero-phase start circuitry for instant phase/frequency acquisition,...
Digitally modulating the injection point in an injection-locked ring oscillator (ILRO) allows it to simultaneously serve as both a multiphase generator and phase interpolator (PI) or rotator. The resulting mostly-digital architecture is compact promises low power nanoscale CMOS, making suitable for multi-Gbps dense I/O applications. This paper describes design considerations such time-modulated ILROs, including tradeoffs associated with determining their strength, modulation frequency,...