A5022080341- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Analog and Mixed-Signal Circuit Design
- Semiconductor Lasers and Optical Devices
- Microwave Engineering and Waveguides
- VLSI and Analog Circuit Testing
- Electromagnetic Compatibility and Noise Suppression
- Photonic and Optical Devices
- Semiconductor materials and devices
- Superconducting and THz Device Technology
- Design Education and Practice
- Optical Network Technologies
- Electrostatic Discharge in Electronics
- ICT Impact and Policies
- Evolutionary Algorithms and Applications
- CCD and CMOS Imaging Sensors
- Advancements in Semiconductor Devices and Circuit Design
- Power Line Communications and Noise
- Low-power high-performance VLSI design
Huawei Technologies (Canada)
2019
Huawei Technologies (United Kingdom)
2018
University of Toronto
2010-2015
University of Waterloo
2014-2015
University of Calgary
2014-2015
University of British Columbia
2014
Gorgias Press (United States)
2014
Queen's University
2006-2007
This paper presents an all-digital background calibration for timing mismatch in time-interleaved analog-to-digital converters (TI-ADCs). It combines digital adaptive estimation and derivative-based correction, achieving lower hardware cost better suppression of tones than previous work. In addition, the first time closed-form exact expressions signal-to-noise distortion ratio (SNDR) a four-channel TI-ADC with after correction are obtained, which can be used to guide design. Simulation...
This paper presents a simulation-based model for the behavior of injection-locked oscillators (ILOs) that can be applied to any oscillator topology under strength injected signal. By using phase domain response (PDR) an oscillator, proposed is shown accurately predict ILOs with asymmetric lock ranges or those injection into multiple locations. It also subharmonic locking behavior. The validated through comparison SPICE simulations as well measured results multiplying ILO fabricated in 65-nm CMOS.
Analog mixed-signal (AMS) receivers for 50+Gb/s PAM-4 offer lower power than ADC-DSP [1]-[3]. Those using DFEs [2]-[3] suffer from relatively high consumption due to the large number of latches needed in speculative DFEs. Better efficiency can be achieved only a CTLE [1]. However, analog front-ends (AFEs) are sensitive variations process, supply voltage and temperature. To combat this while accommodating links with loss exceeding 20dB, an AFE extensive programmability is combined efficient...
This letter presents a 56.25-Gb/s analog-mixed signal pulse amplitude modulation (PAM)-4 receiver in 7-nm fin field effect transistor (FinFET) CMOS. The uses an analog front-end (AFE) with extensive programmability and can equalize channels up to 22.3-dB loss at 14 GHz. AFE settings are optimized using genetic adaptation algorithm find the global minima for bit-error-rate (BER). A PAM-4 clock recovery scheme is proposed that reduces number of required edge samplers bang-bang phase detector...
A new RF model for an AMOS varactor is presented 0.18mum CMOS. This the first reported frequencies above 20 GHz in a standard CMOS technology. It does not rely on boundary conditions different modes of operation and all component values are calculated using clearly defined physical equations, making it easily adaptable to any layout or even other technology nodes. The varactors then implemented as neutralizing capacitances 23 GHz, two-stage, differential low-noise amplifier (LNA) design....
A frequency agile multiplying injection-locked oscillator (MILO) suitable for fast power cycling was designed in 65-nm GP CMOS. Edge detectors and multiple injection sites extend the lock range of x4 multiplier to 36.3% its free-running frequency. Lock is further extended 55.7% (2.3-4 GHz) by using 2 MILOs with adjacent ranges. Monitoring circuits identify correct MILO power-off other within 10 reference clock cycles.
A strategy for the adaptation of an equalizer and variable gain amplifier is presented. Both control signals are generated by examining probability density function (PDF) received data, which obtained from DC output additional analog sampler at output. This technique works to minimize spreading PDF signal while adding only minimal complexity power consumption receiver design. The demonstrated in a wireline fabricated 65-nm CMOS technology. Measured results show that scheme functions...
Single-ended and differential low-noise amplifiers (LNAs), designed in 0.18 μm CMOS for operation at 24 GHz, are introduced this paper. Novel, high-Q series-stub transmission lines (SSTLs) used the matching networks of both LNAs. This SSTL structure shows a notable Q factor improvement over commonly spiral inductor, which helps to minimize losses noise produced LNA networks, making these topologies suitable sensitive receiver front ends. The single-ended amplifier uses two cascade stages...
A broadband preamplifier with gain control and automated common-mode level regulation is presented. It implemented in 65-nm CMOS as part of an analog front-end (AFE) that especially suitable for wireline receivers incorporating digital signal processing or multilevel modulation. S-parameter measurements the receiver show remains well matched to channel impedance across all settings S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> less...
A secondary communication link, or side-channel, is proposed, which uses binary frequency shift keying to modulate the of a high-speed wireline transmitter clock. This side-channel data then received using corresponding receiver's conventional clock and recovery (CDR) circuit. An analysis CDR loop parameters demonstrates that, within certain limits, does not impact signal integrity primary data. Measurements were made on prototype 56-Gb/s PAM-4 (half-rate 14-GHz clock) transceiver in 7-nm...
This paper analyzes the impact of clock skew between comparators in a flash ADC, showing that SNDR penalty introduced by this effect can become significant at high frequencies. To address issue, passive resonant network is proposed to distribute ADC. The inductive termination serves resonate out parasitic and input capacitances allowing for 2.5-GHz signal be conveyed load 256 while consuming less power than traditional networks due reduced number active buffers required. produces little...
What you see before this year, is the result of many years continuous iterative refinement submission process and information processing.This we continue to provide a reduced-featured Digest, in which continuation pages (typically including micrograph occasionally summary data) have been eliminated from print version (only), but are available Digest download IEEE Xplore.To be more-green, use partially recycled paper.Again, with technical editorial group (listed below) under direction...
ReflectionsWhat you see before this year, is the result of many years continuous iterative refinement submission process and information processing.This however, as economic situation persists, we continue to provide a reducedfeatured Digest, in which continuation pages (typically including micrograph occasionally summary data) have been eliminated from print version (only), but are available Digest download IEEE Xplore.Both reduce cost be more-green, use partially recycled paper along with...
This paper proposes a technique for characterization of the frequency-dependent losses in wireline communications link. By using measured jitter at output receiver front-end as its only input, this method is able to estimate both pulse response and frequency link, including effects transmitter output, channel itself, front-end. Simulated results verify accuracy technique, which can be used efficiently adapt settings critical circuit blocks such equalizer tap weights.
The event began with handshakes and catching up friends peers who had not seen one another face to since the COVID-19 pandemic started. IEEE Solid-State Circuits Society (SSCS) Toronto Chapter last held an in-person in October 2019. Judging by smiles record number of attendees (over 70) at this event, there was high demand for nonvirtual activities restart area. All that people needed motivate them leave their home office some free refreshments incredible lineup talented local speakers.
What you see before this year, is the result of many years continuous iterative refinement submission process and information processing.This we continue to provide a simplified printed Digest, in which continuation pages (typically including micrograph occasionally summary data) are not included, but available Digest download IEEE Xplore.In order be more-green, use partially recycled paper.Again, have technical editorial group (listed below) under direction managing editor (Laura Chizuko...