A5024704337- Error Correcting Code Techniques
- Advanced Wireless Communication Techniques
- Analog and Mixed-Signal Circuit Design
- Cooperative Communication and Network Coding
- Neural Networks and Applications
- Radio Frequency Integrated Circuit Design
- Medical Imaging Techniques and Applications
- Advancements in PLL and VCO Technologies
- Coding theory and cryptography
- Wireless Communication Security Techniques
- Radiomics and Machine Learning in Medical Imaging
- Low-power high-performance VLSI design
- Algorithms and Data Compression
- Network Packet Processing and Optimization
- CCD and CMOS Imaging Sensors
- VLSI and Analog Circuit Testing
- Dementia and Cognitive Impairment Research
- Face and Expression Recognition
- Fuzzy Logic and Control Systems
- Advancements in Semiconductor Devices and Circuit Design
- Evolutionary Algorithms and Applications
- DNA and Biological Computing
- Caching and Content Delivery
- Neuroscience and Neural Engineering
- Quantum-Dot Cellular Automata
University of Waterloo
2014-2024
Landscape Research Group
2023
Authorised Association Consortium
2023
University of Arizona Cancer Center
2021
University of Arizona
2021
University of Calgary
2014-2018
University of Toronto
1998-2015
University of British Columbia
2014
Gorgias Press (United States)
2014
University of Alberta
2002-2010
An iterative decoding architecture based on stochastic computational elements is proposed. Simulation results for a simple low-density parity-check code demonstrate near-optimal performance with respect to maximum likelihood decoder. The proposed method provides an alternative analogue high-speed/low-power applications.
This paper presents the design and analysis of a wideband inductorless variable-gain amplifier (VGA) for high-speed communication receiver systems. The proposed methodology using dual-feedback network bandwidth extension dc offset cancellation is analyzed theoretically. proof concept verified by measured stand-alone VGA chip it achieves several record performances compared to existing publications up date. 2.2 GHz 3-dB with wide tuning range from -10 dB 50 dB. Moreover, consumes only 2.5 mW...
Multiple-valued logic has a history that goes back to the 1920s. Its flagship symposium was established in 1971. Despite multiple-valued logic's long history, there have been many recent advances, with several important contributions microelectronic circuits and systems. This tutorial introduction area of survey advances focuses on those contemporary aspects field are most relevant systems community.
Abstract It remains unclear to what extent cerebrovascular burden relates amyloid beta (Aβ) deposition, neurodegeneration, and cognitive dysfunction in mixed disease populations with small vessel Alzheimer's (AD) pathology. In 120 subjects, we investigated the association of vascular (white matter hyperintensity [WMH] volumes) cognition. Using mediation analyses, tested indirect effects WMH on cognition via Aβ deposition ( 18 F‐AV45 positron emission tomography [PET]) neurodegeneration...
LDPC codes are found in many recent communications standards such as 10GBASE-T, DVB-S2 and IEEE 802.16 (WiMAX). We present a review of new class "stochastic" iterative decoding architectures. Stochastic decoders represent probabilistic messages by the frequency ones binary stream. This results simple mapping factor graph code into silicon. An FPGA implementation decoder with 8 information bits coded is described. On an Altera Cyclone FPGA, throughput 5 Mbps when clocked at 100 MHz expected...
A low power inductorless wideband variable gain control amplifier (VGA) for baseband receivers has been designed in a standard digital 90nm CMOS technology. The VGA was implemented using four-stage modified Cherry-Hooper with dual feedback DC-offset canceling network, which simultaneously corrects DC offsets and extends bandwidth without peaking inductor resulting saving the chip space significantly. proposed measured on-chip probing achieves 3-dB of more than 2.2GHz 60dB tuning range. It...
Circuits and an IC implementation of a four-state, block length 16, three-metal one-poly 0.35-μm CMOS analog turbo decoder with fully programmable interleaver are presented. The was tested at 13.3 Mb/s, has 1.2 μs latency, consumes 185 mW on single 3.3-V power supply, resulting in energy consumption 13.9 nJ per decoded bit, thus reducing the by 70% relative to existing digital decoders. core area is 1131.2×1257.9 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This paper presents a stochastic algorithm for iterative error control decoding. We show that the decoding is an approximation of sum-product algorithm. When code's factor graph tree, as with trellises, approaches maximum a-posteriori also demonstrate approximations to alternative update rule successive relaxation. Stochastic decoders have very simple digital implementations which almost no RAM requirements. present example trellis-based Hamming code, and block turbo code constructed from codes
We present a method to design high-throughput fully parallel low-density parity-check (LDPC) decoders. With our method, decoder's longest wires are divided into several short with pipeline registers. Log-likelihood ratio messages transmitted along these pipelined paths thus sent over multiple clock cycles, and the critical path delay can be reduced while maintaining comparable bit error rate performance. The number of registers inserted is estimated by using wiring information extracted from...
Pseudo-NMOS level-shifters consume large static current making them unsuitable for portable devices implemented with HV CMOS. Dynamic help reduce power consumption. To on-current to a minimum (sub-nanoamp), modifications are proposed existing pseudo-NMOS and dynamic level-shifter circuits. A low three transistor design resistive load is also presented.
It is common for a time series dataset to have missing values, and it necessary fill these elements before fitting any model forecasting or prediction. Time imputation remains challenging task due the existence of non-linear dependencies between current past values. Conventional methods, such as deletion rows containing values filling them with last observed value, add bias data are therefore inefficient. There situations where at consecutive points random in dataset, one particular method...
Iterative decoders, including Turbo provide near-optimal error protection for various communication channels and storage media. CMOS analog implementations of these decoders offer dramatic savings in complexity power consumption, compared to digital architectures. Conventional must have supply voltage greater than 1 V. A new low-voltage architecture is proposed which reduces the required by at least 0.4 It shown that can be used implement general sum-product algorithm. The then useful...
This paper presents a novel CMOS impulse radio (IR) ultra-wide-band (UWB) transceiver system design for future contact-less chip testing applications using inductive magnetic coupling as wireless interconnect. The proposed architecture is composed of simple and robust Gaussian monocycle generator at the transmitter, wideband short-range on-chip transformer data transmission, g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosted...
In this paper an implementation of iterative joint detection for multiple access interference using direct-sequence code-division multiple-access (DS-CDMA) is presented. Results field programmable gate array (FPGA) platforms and technology nodes synthesized application specific integrated circuits (ASIC) are The performed a generalized version interleave-division (IDMA) known as partition spreading (PS) CDMA. Decoding methods from turbo sum-product decoding. ASIC system demonstrates maximum...
To date, all published CMOS field-programmable analog array (FPAA) designs have operated under 1 MHz bandwidths. This paper develops circuit methods allowing the development of a FPAA operating at greater than frequencies. For this purpose second-generation current conveyor (CCII) is used. IC test results 0.8 /spl mu/m chip containing four configurable blocks (CABs) based on CCII, as well an interconnection network transmission gates, are presented. The rest show that bandwidths exceed 10...
A single-cycle tree-based 64-bit binary comparator with constant-delay (CD) logic realized in a 65-nm, 1-V CMOS process is presented this paper. Unlike dynamic yet domino-compatible, CD predischarges the output to "0" and conditionally makes transition "1" through critical-path CLK PMOS transistors for an NMOS transistor network. The constant delay (regardless of fan-in) feature it up 2× faster than gate during D-Q mode complex such as two-bit comparator. proposed comparator's architecture...
This paper introduces a self-timed overlapped search mechanism for high-throughput content-addressable memories (CAMs) with low energy. Most mismatches can be found by searching the first few bits in word. Consequently, if word circuit is divided into two sections that are sequentially searched, most match lines second section unused. As faster than an entire word, we could potentially increase throughput initiating second-stage on unused as soon first-stage complete. The realized using...
This paper introduces a reordered overlapped search mechanism for high-throughput low-energy content-addressable memories (CAMs). Most mismatches can be found by searching few bits of word. To lower power dissipation, word circuit is often divided into two sections that are sequentially searched or even pipelined. Because this process, most match lines in the second section unused. Since last very fast compared to rest bits, we propose increase throughput asynchronously initiating...