Silicon integrated circuit spiral inductors and transformers are analyzed using electromagnetic analysis. With appropriate approximations, the calculations reduced to electrostatic magnetostatic calculations. The important effects of substrate loss included in Classic analysis network techniques used derive two-port parameters from circuits. From measurements, low-order, frequency-independent lumped circuits model physical behavior over a broad-frequency range. is applied traditional square...

This paper describes the design and modeling of CMOS transistors, integrated passives, circuit blocks at millimeter-wave (mm-wave) frequencies. The effects parasitics on high-frequency performance 130-nm transistors are investigated, a peak f/sub max/ 135 GHz has been achieved with optimal device layout. inductive quality factor (Q/sub L/) is proposed as more representative metric for transmission lines, standard back-end process, coplanar waveguide (CPW) lines determined to possess higher...

An ultrawideband 3.1-10.6-GHz low-noise amplifier employing an input three-section band-pass Chebyshev filter is presented. Fabricated in a 0.18-/spl mu/m CMOS process, the IC prototype achieves power gain of 9.3 dB with match -10 over band, minimum noise figure 4 dB, and IIP3 -6.7 dBm while consuming 9 mW.

This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into single chip. The has been fabricated in standard 90 nm CMOS process specially designed ESD protection on all mm-wave pads. With 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm 138 receiving. Data transmission up to 5 Gb/s each of I Q channels measured, as data reception over 1 m wireless link at 4 QPSK with less than <sup...

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A broadband inductorless low-noise amplifier (LNA) design that utilizes simultaneous noise and distortion cancellation is presented. Concurrent of the intrinsic third-order from individual stages exhibited with common-gate common-source cascade. The LNA <formula formulatype="inline"> <tex>${\hbox{IIP}}_3$</tex></formula> then limited by second-order interaction between common source gate stages,...

Solution-processed thin-films of semiconducting carbon nanotubes as the channel material for flexible electronics simultaneously offers high performance, low cost, and ambient stability, which significantly outruns organic semiconductor materials. In this work, we report use semiconductor-enriched high-performance integrated circuits on mechanically substrates digital, analog radio frequency applications. The as-obtained thin-film transistors (TFTs) exhibit highly uniform device performance...

A 1.8-GHz LC VCO designed in a 0.18-/spl mu/m CMOS process achieves very wide tuning range of 73% and measured phase noise -123.5 dBc/Hz at 600-kHz offset from carrier while drawing 3.2 mA 1.5-V supply. The impacts wideband operation on start-up constraints are discussed. Tuning is analyzed terms fundamental dimensionless design parameters yielding useful equations. An amplitude calibration technique used to stabilize performance across the band operation. This control scheme not only...

With the availability of 7 GHz unlicensed spectrum around 60 GHz, there is a growing interest in using this resource for new consumer applications requiring very high-data-rate wireless transmission. Historically, cost electronics, implemented compound semiconductor technology, has been prohibitively expensive. A fully integrated CMOS solution potential to drastically reduce costs enough hit price points. System, circuit, and device-level barriers low-cost implementation are described,...

A UWB 3.1 to 10.6 GHz LNA employing an input three-section band-pass Chebyshev filter is reported. Fabricated in a 0.18 /spl mu/m CMOS process, -10 dB over the band, NF of 4 dB, and IIP3 -6.7 dBm while consuming IC achieves power gain 9.3 with match 9 mW.

In recent years, there has been tremendous interest in trying to implement the power amplifier CMOS, due its cost and integration benefits. Most of high (watt-level) CMOS PAs reported date have not exhibited sufficient linearity required for next generation wireless standards. this paper, we report a single-chip linear PA with emerging OFDM-based 4G WiMAX applications. This 90 nm 2.4 GHz uses two-stage transformer-based combiner produces saturated output 30.1 dBm 33% PAE 28 dB small-signal...

A fully integrated 260GHz OOK transceiver is demonstrated in 65nm CMOS. Communication at 10Gb/s has been verified over a range of 40 mm. The Tx/Rx dual on-chip antenna array implemented with half-width leaky wave antennas. Each Tx consists quadrupler driven by class-D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> PA distributed modulator, and outputs +5 dBm EIRP. Rx uses double balanced mixer to down-convert V-band IF signal that...

In this paper, a 240 GHz 16 Gbps QPSK transmitter is demonstrated in 65 nm bulk CMOS process. The chain employs an 80 local oscillator and modulator to generate the data that amplified by class-E switching power amplifier. signal then drives tripler required modulated data. By using on-chip slotted loop antennas, achieves EIRP of 1 dBm. A maximum rate achieved with efficiency 14 pJ/bit.

This paper presents a new approach for power amplifier design using deep submicron CMOS technologies. A transformer based voltage combiner is proposed to combine generated from several low-voltage amplifiers. Unlike other combining transformers, the architecture presented in this provides greater flexibility access and control individual amplifiers combined amplifier. In work, has been utilized output improve average efficiency at back-off. technique does not degrade instantaneous peak...

Operation at millimeter-wave/sub-terahertz frequencies allows one to realize very high data-rate transceivers for wireless chip-to-chip communication. In this paper, a 240 GHz 16 Gbps QPSK receiver is demonstrated in 65 nm CMOS technology. The employs direct-conversion mixer-first architecture with an integrated slotted loop antenna. A LO chain drives the passive mixers down-convert modulated data baseband. baseband signal then amplified using gain, wide bandwidth amplifiers. has noise...

A 60GHz CMOS front-end receiver is described. The comprises an LNA, a quadrature-balanced downconversion mixer, VCO, and frequency doubler. integrated has conversion gain of 11.8dB, NF 10.4dB, input P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> -15.8dBm. implemented in digital 0.13μm process draws 64mA from 1.2V supply.

A fully integrated 5.8 GHz Class AB linear power amplifier (PA) in a standard 90 nm CMOS process using thin oxide transistors utilizes novel on-chip transformer combining network. The combines the of four push-pull stages with low insertion loss over bandwidth interest and is compatible without any additional analog or RF enhancements. With 1 V supply, PA achieves 24.3 dBm maximum output at peak drain efficiency 27% 20.5 dB compression point.

High-resolution mm-wave array beamformers have applications in medical imaging, gesture recognition, and navigation. A scalable architecture for 3D imaging is proposed which single-element phase coherent transceiver (TRX) chips, with programmable TX pulse delay capability, are mounted on a common board to realize the array. This paper presents design of enabling TRX chip: highly integrated 94 GHz phase-coherent pulsed-radar on-chip antennas. The achieves 10 frequency tuning range 300 ps...

Large arrays of radios have been exploited for beamforming and null steering in both radar communication applications, but cost form factor limitations precluded their use commercial systems. This paper discusses how to build that enable multiuser massive multiple-input-multiple-output (MIMO) aggressive spatial multiplexing with many users sharing the same spectrum. The focus is energy- cost-efficient realization these order new applications. Distributed algorithms are proposed, optimum...

This paper describes a low power and element-scalable 60 GHz 4-element phased array transceiver implemented in standard 65 nm CMOS process. Using 1.2 V supply, the consumes <;34 mW/element including LO synthesis distribution. Energy area efficiency are achieved by utilizing baseband phase shifting architecture, holistic impedance optimization, lumped-element based design. Each receiver (RX) element provides 24 dB of gain with an average noise figure (NF) 6.8 while total saturated output...

A 65-nm digitally modulated polar transmitter incorporates a fully integrated, efficient 2.4-GHz switching Inverse Class-D power amplifier. Low-power digital filtering on the amplitude path helps remove spectral images for coexistence. The integrates complete LO distribution network and drivers. Operating from 1-V supply, PA has 21.8-dBm peak output with 44% efficiency. Simple static predistortion meet EVM mask requirements of 802.11g 54-Mb/s WLAN data 18% average

BSIM6 is the latest industry-standard bulk MOSFET model from BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought BSIM4. shows excellent source-drain symmetry during both dc small signal analysis, thus giving results simulations, e.g., harmonic balance simulation. fully scalable with geometry, biases, temperature. has a physical charge-based capacitance including polydepletion quantum-mechanical effect thereby in...

One of the remaining challenges in implementing CMOS 60GHz radios is to cover longer communication distance as high path loss at mm-Wave frequencies demands higher EIRP, which turn requires considerable design effort on transmitter. In addition, comply with OFDM transmitting mode IEEE 802.15.3c standards, power amplifier (PA) must be capable handle a peak level 6~9dB than average without sacrificing reliability. With low supply voltage limitation deeply scaled technologies, efficient...

Two turn-key surface potential-based compact models are developed to simulate multigate transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is double-, triple-, and all-around-gate FinFETs it selected as the world's first industry-standard FinFET. BSIM-IMG (independent-multigate) independent double-gate, ultrathin body (UTB) transistors, capturing dynamic threshold voltage adjustment with back gate bias. Starting from long-channel devices, basic obtained...

A 94-GHz phased-array transceiver IC for frequency modulated continuous wave (FMCW) radar with four transmitters, receivers, and integrated LO generation has been designed fabricated in a 130-nm SiGe BiCMOS technology, into an antenna-in-package module. The transceiver, targeting gesture recognition applications mobile devices, using techniques to reduce the total DC power while still maintaining required link budget FMCW operation. complete array achieves state-of-the-art W-band per-element...

The Green function over a multilayer substrate is derived by solving Poisson's equation analytically in the coordinate and numerically z y coordinates. x functional dependence transformed into discrete cosine transform (DCT) representation for rapid evaluation. further stable form appropriate finite-precision machine This used to solve impedance matrix an arbitrary three-dimensional arrangement of conductors placed anywhere substrate. Using this technique, coupling loss IC circuits can be...