A5058605789- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Silicon Carbide Semiconductor Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Advanced Memory and Neural Computing
- Electrostatic Discharge in Electronics
- MXene and MAX Phase Materials
- Copper Interconnects and Reliability
- Low-power high-performance VLSI design
- Semiconductor materials and interfaces
- Thin-Film Transistor Technologies
- Nanowire Synthesis and Applications
- Radio Frequency Integrated Circuit Design
- Silicon and Solar Cell Technologies
- Electronic and Structural Properties of Oxides
- VLSI and Analog Circuit Testing
- Ferroelectric and Piezoelectric Materials
- 2D Materials and Applications
- Analog and Mixed-Signal Circuit Design
- Electronic Packaging and Soldering Technologies
- Radiation Effects in Electronics
- Metal and Thin Film Mechanics
- Quantum and electron transport phenomena
- GaN-based semiconductor devices and materials
University of California, Berkeley
2016-2025
National Yang Ming Chiao Tung University
2007-2024
Xidian University
2024
Fudan University
2024
Indian Institute of Technology Jodhpur
2023
Nanjing Forestry University
2023
Sichuan Animal Science Academy
2021-2022
Taiwan Semiconductor Manufacturing Company (Taiwan)
2003-2021
Massachusetts Institute of Technology
1974-2019
University of California, Riverside
2019
A flatter route to shorter channels High-performance silicon transistors can have gate lengths as short 5 nm before source-drain tunneling and loss of electrostatic control lead unacceptable leakage current when the device is off. Desai et al. explored use MoS 2 a channel material, given that its electronic properties thin layers should limit such leakage. transistor with 1-nm physical was constructed bilayer single-walled carbon nanotube electrode. Excellent switching characteristics an...
Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy the observed time dependence explained with physical model involving breaking of ≡ Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</inf> H bonds. The device lifetime τ proportional <tex xmlns:xlink="http://www.w3.org/1999/xlink">I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5}</tex> . If I...
A unified flicker noise model which incorporates both the number fluctuation and correlated surface mobility mechanism is discussed. The latter attributed to Coulombic scattering effect of fluctuating oxide charge. has a functional form resembling that theory, but at certain bias conditions it may reduce compatible with Hooge's empirical expression. can unify data reported in literature, without making any ad hoc assumption on generation mechanism. Specifically, predict right magnitude...
We demonstrate field-effect transistors using heterogeneously stacked two-dimensional materials for all of the components, including semiconductor, insulator, and metal layers. Specifically, MoS2 is used as active channel material, hexagonal-BN top-gate dielectric, graphene source/drain contacts. This transistor exhibits n-type behavior with an ON/OFF current ratio >10(6), electron mobility ∼33 cm(2)/V·s. Uniquely, does not degrade at high gate voltages, presenting important advantage over...
A new paradigm of predictive MOSFET and interconnect modeling is introduced. This approach developed to specifically address SPICE compatible parameters for future technology generations. For a given node, designers can use default values or directly input L/sub eff/, T/sub ok/, V/sub t/, R/sub dsw/ dimensions instantly obtain BSIM3v3 customized model early stages circuit design research. Models 0.18 /spl mu/m 0.13 nodes with eff/ down 70 nm are currently available on the web. Comparisons...
The breakdown of thin oxides (7.9-32 nm) subjected to high-field current injection is investigated in this study. physical mechanism found be localized field enhancement at the cathode interface due hole trapping. source trapping believed impact ionization SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> . A quantitative model for oxide based on and presented shown agree well with experimental <tex...
The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in very-short-channel-length range, previously reported exponential dependence on length linear voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account effects gate oxide thickness, source/drain junction depth, doping, describe accelerated th/ due their...
The dependence of the metal gate work function on underlying dielectric in advanced metal-oxide-semiconductor (MOS) stacks was explored. Metal functions high-κ dielectrics are observed to differ appreciably from their values SiO2 or vacuum. We applied interface dipole theory between and a MOS transistor obtained excellent agreement with experimental data. Important parameters such as slope for like SiO2, Al2O3, Si3N4, ZrO2, HfO2 were extracted. In addition, we also explain weaker n+ p+...
In this paper, we propose a novel operation of MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in Silicon-On-Insulator (SOI) technology. device, the threshold device function its gate voltage, i.e., as increases (V/sub t/) drops resulting much higher current drive than standard low-power supply voltages. On other hand, V/sub t/ high at gs/=0, therefore leakage low. We provide extensive experimental results...
The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although result can be interpreted terms electron temperature as well. This results a relatively simple expression that quantitatively predict current MOSFET's. model compared with measurements on series MOSFET's and good agreement achieved. In process, new values for many physical parameters such scattering mean-free-path, impact-ionization energy are determined. Of...
The influence of top electrode material on the resistive switching properties ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based memory film using Pt as a bottom was investigated in this letter. In comparison with Pt/ZrO /Pt and Al/ZrO devices, Ti/ZrO device exhibits different current-voltage (I- V) curve, which can be traced reproduced by dc voltage more than 1000 times only showing little decrease resistance ratio between high...
A simple and sensitive method of measuring the thermally induced index changes arising from absorption a laser beam in low-loss material is described. The sample placed outside cavity, but at position minimum radius curvature wavefront, which confocal distance behind waist. It estimated that enough to measure coefficients order 5 x 10(_6) cm(_1) it shown experimentally have good accuracy on materials. detailed comparison sensitivity estimates given for various published thermal-lens methods...
Two-dimensional materials present a versatile platform for developing steep transistors due to their uniform thickness and sharp band edges. We demonstrate 2D-2D tunneling in WSe2/SnSe2 van der Waals vertical heterojunction device, where WSe2 is used as the gate controlled p-layer SnSe2 degenerately n-type layer. The gap facilitates regulation of alignment at heterojunction, without necessity barrier. ZrO2 dielectric, allowing scaling oxide improve device subthreshold swing. Efficient...
In this work, we report the first Negative-Capacitance FinFET. ALD Hf042Zr058O2 is added on top of FinFET's gate stack. The test devices have a floating internal that can be electrically probed. Direct measurement found small-signal voltage amplified by 1.6X maximum at in agreement with improvement subthreshold swing (from 87 to 55mV/decade). ION increased >25% for IOFF. For time, demonstrate raising HfZrO2 ferroelectricity, annealing higher temperature, reduces and eliminates IV hysteresis...
We report subthreshold swings as low 8.5 mV/decade over high eight orders of magnitude drain current in short-channel negative capacitance FinFETs (NC-FinFETs) with gate length <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{g}=100$ </tex-math></inline-formula> nm. NC-FinFETs are constructed by connecting a high-quality epitaxial bismuth ferrite (BiFeO <sub...
Abstract Single-crystalline thin films of complex oxides show a rich variety functional properties such as ferroelectricity, piezoelectricity, ferro and antiferromagnetism so on that have the potential for completely new electronic applications. Direct synthesis silicon remains challenging because fundamental crystal chemistry mechanical incompatibility dissimilar interfaces. Here we report integration (down to one unit cell) single crystalline, oxide onto substrates, by epitaxial transfer...
We study the effects of variation ferroelectric material properties (thickness, polarization, and coercivity) on performance negative capacitance FETs (NCFETs). Based this, we propose concept conservative design NCFETs, where any unintentional yet reasonable simultaneous ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim \pm 3$ </tex-math></inline-formula> %) in parameters does not result emergence...
We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cycles. The (FeFETs) incorporate high- κ interfacial layer (IL) of thermally grown nitride (SiN <sub xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> ) and thin 4.5 nm Zr-doped FE-HfO xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) ~30 insulator (SOI) channel. device...
High performance PMOSFETs with gate length as short 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the channel effect. 45 nm gate-length PMOS FinEET has an I/sub dsat/ of 410 /spl mu/A//spl mu/m (or 820 depending on definition width a device) at Vd=Vg=1.2 V and Tox=2.5 nm. The quasi-planar nature this variant MOSFETs makes device fabrication relatively easy using conventional planar process technologies. Simulation shows possible scaling 10-nm length.
The random telegraph noise exhibited by deep-submicrometer MOSFETs with very small channel area (<or=1 mu m/sup 2/) at room temperature is studied. Analysis of the amplitude current fluctuations reveals that trapped charges generate through modulation carrier mobility in addition to number. Parameters needed for modeling fluctuation effect on flicker conventional are extracted directly from data.<<ETX>>
Significant drain leakage current can be detected at voltages much lower than the breakdown voltage. This subbreakdown dominate zero V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> in thin-oxide MOSFET's. The mechanism is shown to band-to-band tunneling Si drain/gate overlap region. In order limit 0.1 pA/µm, oxide field gate-to-drain region must limited 2.2 MV/cm. may set another constraint for thickness or power supply
High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical SOI features: 1) a transistor channel which formed on surfaces of an ultrathin Si fin and controlled by gate electrodes both sides fin; 2) two gates each other source/drain (S/D) regions; 3) raised S/D 4) short (50 nm) maintain quasi-planar topology for ease fabrication. The 45-nm p-channel FinFET showed I/sub...