MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si/sub 0.4/Ge/sub 0.6/ as material, desired threshold voltage was achieved for ultrathin body device. The quasiplanar nature of this new variant vertical can be fabricated relatively easily conventional planar MOSFET process technologies.

High performance PMOSFETs with gate length as short 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the channel effect. 45 nm gate-length PMOS FinEET has an I/sub dsat/ of 410 /spl mu/A//spl mu/m (or 820 depending on definition width a device) at Vd=Vg=1.2 V and Tox=2.5 nm. The quasi-planar nature this variant MOSFETs makes device fabrication relatively easy using conventional planar process technologies. Simulation shows possible scaling 10-nm length.

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical SOI features: 1) a transistor channel which formed on surfaces of an ultrathin Si fin and controlled by gate electrodes both sides fin; 2) two gates each other source/drain (S/D) regions; 3) raised S/D 4) short (50 nm) maintain quasi-planar topology for ease fabrication. The 45-nm p-channel FinFET showed I/sub...

Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported. To improve the short channel effect immunities, a novel folded transistor structure is proposed. The quasi-planar nature of this new variant vertical double-gate SOI simplified fabrication process. special features are: (1) formed in ultra-thin Si fin and controlled by double-gate, which suppresses effects; (2) two gates self-aligned aligned S/D; (3) S/D raised reduce parasitic resistance; (4) low-temperature or...

A fully depleted lean channel transistor (DELTA) having a gate structure and vertical ultrathin SOI (silicon-on-insulator) with selective field oxide is reported. In the deep submicron region, oxidation useful for achieving isolation. It provides high-quality crystal Si-SiO/sub 2/ interface as good those of conventional bulk single-crystal devices. Using experiments simulation, it was shown that DELTA has effective controllability its (<0.2- mu m) superior device characteristics, e.g....

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed reduce data transmission delay. speed improvement of 20 ns was achieved when utilizing power supply. An accurate speed-enhanced half-V/sub CC/ generator current-mirror amplifier tri-state buffer proposed. With it, response time reduction about 1.5 decades realized....

A fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultrathin silicon-on-insulator (SOI) structure is presented. In the deep-submicrometer region, selective oxidation produces and isolates an SOI MOSFET that has high crystalline quality, as good of conventional bulk single-crystal devices. Experiments three-dimensional simulations have shown this effective control provides superior device characteristics: reduction in short-channel effects,...

A fully depleted lean-channel transistor (DELTA) that has a gate with vertical ultrathin SOI structure is reported. In the deep submicrometer region, selective oxidation useful in realizing isolation. It provides high crystalline quality, as good of conventional bulk single-crystal devices. Using experiments and three-dimensional simulation, it was shown effective channel controllability its superior device characteristics.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML"...

We examined, both experimentally and theoretically, the mobility reduction in metal-insulator-semiconductor field-effect transistors (MISFETs) limited by remote charge scattering. The accuracy of calculations was confirmed agreement with experiments on MISFETs pure SiO2 gate dielectrics, which is reduced due to scattering from depletion charges polycrystalline silicon gate. In Al2O3∕SiO2 stacks, we could not identify contributions phonon using low-temperature measurements mobility....

Chemical-mechanical-polishing (CMP) was used to smooth the surface of a SiGe substrate, on which strained-Si n- and p-MOSFETs were fabricated. By applying CMP after growing buffer layer, roughness considerably reduced, namely, 0.4 nm (rms). A layer then successfully grown CMP-treated substrate. The fabricated MOSFETs showed good turn-off characteristics, (i.e., equivalent those Si control devices). Moreover, capacitance-voltage (CV) measurements revealed that quality gate oxide devices same...

Ultra-thin single crystal silicon with the (100) surface formed by local-oxidation-of-silicon (LOCOS) on a silicon-on-insulator (SOI) substrate becomes quasi-direct band-gap semiconductor due to quantum mechanical confinement effect. The device is simple pn diode in planar structure. Electro-luminescence (EL) has been observed lateral carrier injections into two-dimensional well.

To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, activation energy (Ea) and field acceleration factor SiC n-channel MOS (nMOS) p-channel (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress range 25–350 °C. Ea around 300 °C was 0.7 eV for nMOS 0.66 pMOS, which about twice as high that below 150 did not differ greatly depending on conductivity type. The gate mechanism shifted from 1/E model to E...

From a practical fabrication point of view, FD/DG-SOI MOSFETs were examined as deep-sub-tenth /spl mu/m devices. Solutions for the critical issues ultra-thin layer resistance, threshold voltage control, and double-gate formation discussed with respect to device scalability. By showing feasibility based on experimental data, it was made clear that would become viable approach overcoming CMOS scaling limit.

A low-voltage circuit technology for 1.5-V, 64-Mb DRAMs designed to achieve a reasonable speed performance projected from existing trends is described. The DRAM has been deigned using novel circuits. An RAS access time of 50 ns obtained with power dissipation as low 44 mW. These results show that battery-operated promising target the future

FinFET split-gate metal-oxide nitride oxide silicon (SG-MONOS) Flash memories have been fabricated and operated for the first time. Excellent subthreshold characteristics small threshold-voltage variability owing to a Fin-structure are clarified. It is demonstrated that Fin top-corner effects well suppressed by incremental step pulse programming source side injection. Highly reliable data retention at 150 °C after 250K program/erase cycles confirmed advanced automotive system applications.

We characterized the excited state (ES) and ground (GS) of negatively charged silicon vacancy (VSi−) centers in hexagonal carbide (4H-SiC) using optically detected magnetic resonance (ODMR) to realize thermometric quantum sensors. report observation inverted contrast between ODMR signals ES GS clarify effect energy sublevels spin states 4H-SiC. confirm that VSi− are dependent on temperature with a thermal shift 2 MHz/K zero-field splitting (ZFS). Thus, we fabricated microscale dots 4H-SiC...

This paper presents a metal-insulator-metal capacitor for SoC applications which has the highest capacitance density (up to 12 fF//spl mu/m/sup 2/) ever reported device in this field. The simple MIM structure allowed development of process as single-mask add-on conventional Cu BEOL processing.

We examined effects of the remote surface roughness, which is roughness between polycrystalline silicon gate and dielectric, on inversion carrier mobility metal-insulator-semiconductor field-effect-transistors with ultrathin dielectrics. calculated effective by linear response theory found that scattering from reduces especially at high vertical fields. The severely reduced, if correlation length comparable to inverse thermal de Broglie wave number. show hole reduction experimentally for...

The authors propose a light-emitting field-effect transistor with the active layer made of ultrathin single crystal silicon (100) surface orientation. ambipolar carrier injections from highly impurity doped regions to are achieved in complementary-metal-oxide-semiconductor compatible planar structures and optical intensities controlled by gate voltage. By using device, they have demonstrated that simple electrical signal can be transferred light detected on same chip as photocurrents bias.

We describe the observation of stimulated emissions by current injections into a silicon quantum well. The device consists free standing membrane with distributed feedback resonant cavity fabricated state-of-the-art processes. emission spectra have multimode structures peaked in near-infrared region above submilliampere threshold currents at room temperatures. Consequently, electronics and photonics should be able to converged on chips using well laser diodes.

Abstract We developed a 16 x 8 quantum dot array and CMOS circuit hybrid chip (Q-CMOS). By optimizing the transistor design of Q-CMOS formed by fully depleted (FD)-SOI, it is possible to selectively control each dots, obtained characteristics variation for first time. Due mesoscopic effect, in dots larger than threshold voltage transistors. Thus, we have an important finding that necessary suppress variability order realize large-scale computer. also confirmed change depending on applied...

A self-aligned stacked-capacitor cell called the CROWN (a crown-shaped cell), used for experimental 64-Mb-DRAMs operated at 1.5 V, has been developed using 0.3- mu m electron-beam lithography. This memory an area of 1.28 m/sup 2/. The word-line pitch and sense-amplifier this are 0.8 1.6 m, respectively. In spite small area, a large capacitor surface 3.7 2/ because (1) it electrode, (2) its is on data line, (3) fabrication process structure. Ta/sub 2/O/sub 5/ film equivalent to 2.8-nm SiO/sub...

The alpha -particle-induced soft-error phenomena for VLSIs are investigated using a three-dimensional device simulator and new experimental method. scope of the present work includes description of: scalability funneling length (size effects proximity effects), reduced supply voltages, potential barrier effect an n/sup +/-p/sup +/-p (substrate) structure, compulsory exposure experiments, that causes soft error ( -particle source-drain penetration effect, or ALPEN). A behavior cannot be...

The Random Telegraph Noise (RTN) in an advanced Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is considered to be triggered by just one electron or hole, and its importance recognised upon the aggressive scaling. However, detailed nature of charge trap remains investigated due difficulty find out exact device, which shows RTN feature over statistical variations. Here, we show can observed from virtually all devices at low temperatures, provide a methodology enable systematic way...

We propose a structure with word/bit line control for two-dimensional quantum dot array, which allows random access arbitrary dots small number of signals. To multiple single signal, every should have wide operating voltage allowance to overcome the property variations. fabricate arrays using silicon-complementary-metal-oxide-semiconductor technology an alternating dual-standard gate oxide thickness. The are designed allowable window 0.2 V electrons, is one order magnitude wider than that...