A5004986126- Ferroelectric and Negative Capacitance Devices
- Semiconductor materials and devices
- Advanced Memory and Neural Computing
- Ferroelectric and Piezoelectric Materials
- MXene and MAX Phase Materials
- Magnetic Properties and Applications
- 2D Materials and Applications
- Cardiac Structural Anomalies and Repair
- Electric Power Systems and Control
- Advancements in Semiconductor Devices and Circuit Design
- Acoustic Wave Resonator Technologies
University of California, Berkeley
2014-2019
Massachusetts Institute of Technology
2019
University of California, Riverside
2019
Australian National University
2019
Stanford University
2019
To further reduce the power dissipation in nanoscale transistors, fundamental limit posed by Boltzmann distribution of electrons has to be overcome. Stabilization negative capacitance a ferroelectric gate insulator can used achieve this boosting transistor voltage. Up now, is only directly observed polymer and perovskite ferroelectrics, which are incompatible with semiconductor manufacturing. Recently discovered HfO 2 ‐based on other hand, ideally suited for application because their high...
We report subthreshold swings as low 8.5 mV/decade over high eight orders of magnitude drain current in short-channel negative capacitance FinFETs (NC-FinFETs) with gate length <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{g}=100$ </tex-math></inline-formula> nm. NC-FinFETs are constructed by connecting a high-quality epitaxial bismuth ferrite (BiFeO <sub...
Negative capacitance (NC) FETs with channel lengths from 30 nm to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50~\mu \text{m}$ </tex-math></inline-formula> , gated ferroelectric hafnium zirconium oxide are fabricated on fully depleted silicon-on-insulator (FDSOI) substrates. Enhanced due NC, hysteresis-free operation, and improved subthreshold slope observed. The NC effect leads enhancement of drain...
We present a simulation study of the negative capacitance effect incorporating leakage through ferroelectric (FE) capacitor. The dynamics FE is modeled using Landau-Khalatnikov equation. When an and dielectric are simply connected in series without metal contact between them, stabilization remains unchanged irrespective leakage. However, when used, any finite makes it impossible to stabilize at steady state. Nonetheless, voltage applied, configuration enters state as long gate cycled faster...
We report on negative capacitance FETs (NCFETs) with a 1.8-nm-thick Zr-doped HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate oxide layer fabricated an FDSOI wafer. Hysteresis-free operation is demonstrated. When compared to baseline that uses the same thickness, subthreshold swing (SS) steeper by more than 20 mV/decade and larger 10X reduction in OFF current ( <inline-formula xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math...
We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.8</sub> Zr xmlns:xlink="http://www.w3.org/1999/xlink">0.2</sub> O xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) fabricated using self-aligned last process. The FETs are silicon-on-insulator wafers, and the is deposited atomic layer deposition. reported devices have an ON/OFF...
The emergence of negative capacitance as a way to limit power dissipation in CMOS logic transistors has raised the question response delay ferroelectric capacitance. Latency requirements for digital require time on order 10 ps or less. In this letter, we establish coherent theoretical framework analyze between clock edge at gate and semiconductor channel transistor. standard Landau-Khalatnikov equation approximates slow, diffusive classical motion. Therefore, using it predict speed is...
In this work, we present an experimental demonstration of a content addressable memory (CAM) cell based on ferroelectric HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> field effect transistors (FeFETs). Our proposed CAM (FeCAM) utilizes CMOS-compatible material, hafnium zirconium oxide (HZO), as the gate dielectric. We discuss operation FeCAM and propose suitable architecture to realize in-memory computation well single clock cycle...
We report on negative capacitance (NC) FinFETs with ferroelectric Hf <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</inf> Zr O xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> (HZO) as gate dielectric fully depleted silicon insulator (FDSOI) substrate various channel length (L xmlns:xlink="http://www.w3.org/1999/xlink">CH</inf> ) of 450 nm to 30 and multiple fin widths (W xmlns:xlink="http://www.w3.org/1999/xlink">FIN</inf> 200 nm....
We investigate the impact of inner fringing fields on negative capacitance FinFET (NC-FinFET) and how this scales with technology node. The 8-/7-nm node p-type body NC-FinFET is modeled using Sentaurus technology-aided design (TCAD), which couples Poisson Landau equations. It found that NC effect beneficial for device scaling. OFF current well suppressed in short-channel devices (64.4% reduction at L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
We report Negative Capacitance nFETs with a ~ 1 nm effective oxide thickness (EOT) gate stack. Experimental measurements show clear steepening of the slope I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -V xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> characteristic in weak inversion regime, indicating that capacitance matching takes place there. This leads to non-linear behavior current log scale, which is not observed...
It is well known that one needs an external source of energy to provide voltage amplification. Because this, conventional circuit elements such as resistors, inductors or capacitors cannot amplification all by themselves. Here, we demonstrate a ferroelectric can cause differential without needing source. As the switches from polarization state other, transfer takes place dielectric, determined ratio their capacitances, which, in turn, leads {This very different nature inductor-capacitor...
We report on the measurement of a 101-stage ring oscillator (RO) consisting state-of-the-art 14 nm FinFET devices with ferroelectric gate layer that exhibits negative capacitance. show stage delay as function applied voltage can be directly modeled from DC characteristics individual NC-nFET and NC-pFET constitute RO, thereby demonstrating there is no slowdown NC effect at highest speed tested - per-stage small 7.2 ps.
The ability to partially switch an FeFET could enable their use as embedded low-voltage memory and analog weight storage in artificial neural networks (ANNs). We report on characterization of FeFETs gated with 5.5-nm Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.8</sub> Zr xmlns:xlink="http://www.w3.org/1999/xlink">0.2</sub> O xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , fabricated fully depleted silicon-on-insulator using a...
We examine the nature of interface states induced during integration ferroelectric hafnium zirconium oxide on silicon. Metal-ferroelectric-insulator-silicon capacitors, with a thin layer grown by atomic deposition as and various interfacial layers insulator, are investigated. Since high-temperature post-annealing is necessary to induce formation phase in this stack, integrity oxide/silicon must be preserved after processing. As such, we show that nitrided interlayer provides an improved...
Continuum phase-field simulations show how a multidomain ferroelectric capacitor in series with resistor can exhibit transient response which the behaves as negative capacitor. We that accelerating domain growth leads to capacitance (NC), and this happens even when there is no initial switching of domains. The observed behavior close agreement experimental results NC transients seen recently number material systems.
A Monte Carlo TCAD simulation study of the impact polycrystallinity and dielectric phases ferroelectric film on an 8/7 nm node NC-FinFET is presented. The considers random variation remnant polarization <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\boldsymbol{P_{r}})$</tex> presence phases. In order to keep ferroelectric-film induced device variability less than those by other sources (RDF, GER, FER, MGG), we found that DE content must be...
We have studied the effect of Zr doping, from 0% to 100%, on ferroelectric properties HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . Amorphous Hf xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> O TiN and Si substrates is deposited using atomic layer deposition (ALD) then annealed in a rapid thermal processing (RTP) tool while capped by 20 nm sputtered TiN. Based our...
A complete simulation framework is presented for Negative Capacitance FinFETs including Numerical Simulation, Compact Modeling, and Circuit Evaluation. 2D Simulation coupled with the Landau’s Ferroelectric Model captures device characteristics. new version of distributed Negative-Capacitance FinFET also in this work, where influence short-channel effects voltage amplification are newly incorporated. Finally, a detailed analysis, from an energy perspective, gate ring-oscillator circuits.
We investigate negative capacitance transients-the time period during ferroelectric switching when the voltage across a changes in direction opposite to that of charge-by constructing simple series network an isolated single crystalline capacitor and external resistor. A study dynamics such circuit reveals scale this phenomenon is controlled by resistor rather than material dependent intrinsic speeds. As canonical approach for directly measuring capacitance, these experiments could guide...