Computational RAM is a processor-in-memory architecture that makes highly effective use of internal memory bandwidth by pitch-matching simple processing elements to columns. can function either as conventional chip or SIMD (single-instruction stream, multiple-data stream) computer. When used memory, computational competitive with DRAM in terms access time, packaging and cost. Adding logic not question bolting together two existing designs. The paper considers how integrates power using an...

In this paper, a fixed-point finite impulse response adaptive filter is proposed using approximate distributed arithmetic (DA) circuits. design, the radix-8 Booth algorithm used to reduce number of partial products in DA architecture, although no multiplication explicitly performed. addition, are approximately generated by truncating input data with an error compensation. To further hardware costs, Wallace tree considered for accumulation products. As result, delay, area, and power...

Abstract Difficulty in making low noise magnetic measurements is a significant challenge to the use of cube‐satellite (CubeSat) platforms for scientific constellation class missions study magnetosphere. Sufficient resolution required resolve three‐dimensional spatiotemporal structures field variations accompanying both waves and current systems nonuniform plasmas controlling dynamic magnetosphere‐ionosphere coupling. This paper describes design, validation, test flight‐ready, miniature,...

In this letter, a compact substrate-integrated waveguide (SIW) notched-septum polarizer is designed, manufactured, and tested. Metalized slots are used instead of vias in proximity to the notches improve polarization purity. An impedance matching bandwidth 7.9% at 29 GHz transmission coefficient better than -1.6 dB demonstrated. The axial ratio less 3 over 4.5% (sufficient for 5G). implementation an array antenna was measured validate its reliability applications. Given performance small...

This paper proposes charge pumps with improved power efficiency suitable for low-power on-chip applications. Undesired transfer, which has a direction opposite to that of the intended current flow, presents significant source loss in pumps. The proposed pump circuit utilizes transfer switches complementary branch scheme significantly reduce undesired thereby improving and increasing output voltage effectively. An optimized gate control strategy is applied further decrease caused by transfer....

We present an inexpensive hand-held device (240 g) that implements microchip isotachophoresis (ITP) with laser induced fluorescence (LIF) detection. This self-contained instrument integrates the functionality required for high voltage generation onto a microelectronic chip, includes LIF detection and is powered by universal serial bus (USB) link connected to laptop computer. Using this we demonstrate focusing of fluorescent species limit 100 pM. show response detector linear initial analyte...

Pseudo-NMOS level-shifters consume large static current making them unsuitable for portable devices implemented with HV CMOS. Dynamic help reduce power consumption. To on-current to a minimum (sub-nanoamp), modifications are proposed existing pseudo-NMOS and dynamic level-shifter circuits. A low three transistor design resistive load is also presented.

Vector quantization (VQ) is a general data compression technique that has scalable implementation complexity and potentially high ratio. In this paper, novel of VQ using stochastic circuits proposed its performance evaluated against conventional binary designs. The designs are compared for the same quality, synthesized an industrial 28-nm cell library. effects varying sequence length representation studied with respect to throughput per area (TPA) energy operation (EPO). implementations...

The 2001 ITRS roadmap predicts continued aggressive progress towards deep submicron linewidths for at least the next 15 years. In this article we describe results of a simulation study into effects crosstalk among DRAM wordlines and bitlines present future technology nodes predicted by roadmap. An analog simulator was used to solve associated transmission line equations derived from Maxwell's in time domain. Hence, not only considered interconnect resistances capacitances, but also...

Electrophoresis is a mainstay of lab-on-a-chip (LOC) implementations molecular biology procedures and the basis many medical diagnostics. High voltage (HV) power supplies are necessary in electrophoresis instruments significant part overall system cost. This cost instrumentation impediment to making LOC technologies more widely available. We believe one approach overcoming this problem use microelectronic technology (complementary metal-oxide semiconductor, CMOS) generate control HV. present...

We demonstrate a new and extremely inexpensive, multipurpose desktop system for operating lab-on-a-chip (LOC) devices. The provides all of the infrastructure necessary genetic amplification analysis, with orders magnitude improvement in performance over our previous work. A modular design enables high levels integration while allowing scalability to lower cost smaller size. component this is ca. $600, yet it could support many diagnostic applications. an implementation via polymerase chain...

The authors report on the development and characterization of a plasma etching method that utilizes process steps common to both well-known Bosch cryogenic deep reactive ion methods for silicon. This hybrid uses cyclical etch alternate between passivating chemistries as in process, while still maintaining sample temperatures at −100°C cryogenically cooled stage. advantages this are superior control wall profiles isolated features, minimization grass formation, elimination an expensive gas,...

Capillary electrophoresis is a cornerstone of lab-on-a-chip (LOC) implementations for medical diagnostics. However, the infrastructure needed to operate electrophoretic LOC tends be large and expensive, hindering development portable or low-cost systems. A custom-designed highly integrated microelectronic chip high-voltage generation switching interfacing recently developed. Here, authors integrate with microfluidic chip, solid-state laser, filter, lens several dollars worth electronic...

A TEM horn antenna with modified radiation pattern customized for oil well monitoring application is presented in this paper. The designed to operate an saturated medium the frequency range between 1.4 11 GHz. complete design procedure proposed a method modify introduced here. modification conducted using nonuniform expansion of flares. Applying technique eliminates ripples antenna's main-lobe at higher frequencies, problem which exists conventional antennas. coefficients control flare...

We present a design methodology for synchronous single-rail domino logic circuits, where inverting and nonmonotonic functions can be integrated into pipeline with almost zero overhead relative to classic counterparts. This family, called clock-logic (CL) domino, is functionally complete while tolerating skew minimizing the number of clock phases that must distributed. Simulation results CL algorithmic unit (ALU) at 1 GHz under high conditions, shows power reduction 41% over same ALU...

A high-voltage microfluidic controller designed using DALSA semiconductor's 0.8-mum low-voltage/high-voltage complementary metal-oxide semiconductor/double diffused semiconductor process is presented. The chip's four output drivers can switch 300 V, and the dc-dc boost converter generate up to 68 V external passive components. This integrated circuit represents an advancement in technology when used conjunction with a charge coupling device (CCD)-based optical system glass channel, enabling...

Reliable microfabrication processes and materials compatible with complementary metal-oxide semiconductor (CMOS) technology are required by industry for the mass production of complex highly miniaturized lab-on-a-chip systems. Photopolymers commonly used in industry, suitable integration multilayer structures onto CMOS substrates. This paper describes a novel photopolymer bonding process fabrication three-dimensional monolithic microfluidic devices. The consists formation conformal adsorbate...

Low-density parity-check convolutional codes (LDPC-CCs) complement their popular block-oriented counterparts and may be more suitable in certain communication applications. These include streaming voice, video, packet switching networks. In order to use these efficiently we must generate termination sequences similar those used conventional codes. this paper, present a construction method for sequence generation circuits field-programmable gate arrays application-specific integrated...

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Low-density parity-check block codes (LDPC-BCs) are quickly becoming the forward error correcting code of choice for emerging communication standards. However, low-density convolutional (LDPC-CCs), counterpart LDPC-BCs, seem to be better suited in applications with streaming data or variable sized packets. A rate-1/2, (128,3,6) LDPC-CC ASIC has been implemented 180-nm, 1.8-V CMOS technology. We...

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A novel design approach is proposed for low-density parity-check convolutional codes (LDPC-CCs), that jointly optimizes the code, encoder and decoder to achieve high-throughput parallel encoding decoding. series of implementation-oriented constraints are applied construct architecture-aware (AA) by introducing algebraic structures into matrix. The resulting AA have bit error rate performance...

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We present a rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder that we implemented in 90-nm CMOS process. The 1.1-Gb/s is compact, low-power implementation includes one-hot encoding for phase generation built-in termination. design uses memory-based interface with minimum number of memory banks to deliver an information throughput 1 b per clock cycle. shares one controller among...