Approximate computing has been considered to improve the accuracy-performance tradeoff in error-tolerant applications. For many of these applications, multiplication is a key arithmetic operation. Given that approximate compressors are element design power-efficient multipliers, we first propose an initial 4:2 compressor introduces rather large error output. However, number faulty rows compressor's truth table significantly reduced by encoding its inputs using generate and propagate signals....

The lifting scheme reduces the computational complexity of discrete wavelet transform (DWT) by factoring filters into cascades simple steps that process input samples in pairs. We propose four compact and efficient hardware architectures for implementing lifting-based DWTs, namely, one-dimensional (1-D) two-dimensional (2-D) versions what we call recursive dual scan architectures. 1-D architecture exploits interdependencies among coefficients interleaving, on alternate clock cycles using...

Improving the accuracy of a neural network (NN) usually requires using larger hardware that consumes more energy. However, error tolerance NNs and their applications allow approximate computing techniques to be applied reduce implementation costs. Given multiplication is most resource-intensive power-hungry operation in NNs, economical multipliers (AMs) can significantly In this article, we show AMs also improve NN by introducing noise. We consider two categories AMs: 1) deliberately...

Multiplication is the most resource-hungry operation in neural networks (NNs). Logarithmic multipliers (LMs) simplify multiplication to shift and addition operations thus reduce energy consumption. Since implementing logarithm a compact circuit often introduces approximation, some accuracy loss inevitable LMs. However, this inaccuracy accords with inherent error tolerance of NNs their associated applications. This article proposes an improved logarithmic multiplier (ILM) that, unlike...

Logarithmic multipliers take the base-2 logarithm of operands and perform multiplication by only using shift addition operations. Since computing is often an approximate process, some accuracy loss inevitable in such designs. However, area, latency, power consumption can be significantly improved at cost loss. This paper presents a novel method to log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> N that, unlike existing approaches,...

A compact, fast, and accurate realization of a digital Gaussian variate generator (GVG) based on the Box-Muller algorithm is presented. The proposed GVG has faster sample generation rate higher tail accuracy with lower hardware cost than published designs. design can be readily configured to achieve arbitrary (i.e., 16-bit datapath up plusmn15 times standard deviation sigma) only small variations in utilization, without degrading output rate. Polynomial curve fitting utilized along hybrid...

Random number generators are an essential part of cryptographic systems. For the highest level security, true random (TRNG) needed instead pseudorandom generators. In this paper, stochastic behavior spin transfer torque magnetic tunnel junction (STT-MTJ) is utilized to produce a TRNG design. A parallel structure with multiple MTJs proposed that minimizes device variation effects. The design validated in 28-nm CMOS process Monte Carlo simulation using compact model MTJ. National Institute...

In the Internet of Things era, security concerns may require a cryptography system in every connected device. True random number generators (TRNGs) are preferred instead pseudorandom systems to achieve higher level security. For on-chip applications, we seek scalable and CMOS-compatible devices designs for TRNGs. this paper, stochastic behavior spin transfer torque magnetic tunnel junction (STT-MTJ) is utilized source randomness. However, variations correlations exist MTJs due fabrication...

This article describes a significantly improved sum-of-sinusoids-based model for the accurate simulation of time-correlated Rayleigh and Rician fading channels. The proposed utilises random walk processes instead variables some sinusoid parameters to more accurately reproduce behaviour wireless radio propagation. Every block generated using our has statistical properties on its own hence, unlike previously models, there is no need time-consuming ensemble-averaging over multiple blocks. Using...

The 2001 ITRS roadmap predicts continued aggressive progress towards deep submicron linewidths for at least the next 15 years. In this article we describe results of a simulation study into effects crosstalk among DRAM wordlines and bitlines present future technology nodes predicted by roadmap. An analog simulator was used to solve associated transmission line equations derived from Maxwell's in time domain. Hence, not only considered interconnect resistances capacitances, but also...

A channel simulator is an essential component in the development and accurate performance evaluation of wireless systems. Two major approaches have been widely used to produce statistically fading variates, namely shaping flat spectrum Gaussian variates using digital filters sum-of-sinusoids (SOS)-based methods. Efficient design implementation techniques for these schemes are particular importance verification systems with a relatively large number channels, such as ad hoc networks. This...

Emulation of fading channels is a key step in the design and verification wireless communication systems. Testing transceivers with actual inconvenient due to unrepeatable uncontrollable channel conditions. In this paper we present compact field-programmable gate array (FPGA) implementation for circuit that generates temporally-correlated variates emulating multipath radio channels. The implemented emulator flexible enough model different propagation scenarios accurately it can be on same...

Vector quantization (VQ) is a general data compression technique that has scalable implementation complexity and potentially high ratio. In this paper, novel of VQ using stochastic circuits proposed its performance evaluated against conventional binary designs. The designs are compared for the same quality, synthesized an industrial 28-nm cell library. effects varying sequence length representation studied with respect to throughput per area (TPA) energy operation (EPO). implementations...

Triple-modular redundancy (TMR), which consists of three identical modules and a voting circuit, is common architecture for soft-error tolerance. However, the original TMR suffers from two major drawbacks: large area overhead vulnerability voter. In order to overcome these drawbacks, we propose new complementary dual-modular (CDMR) scheme mitigating effect soft errors. Inspired by Markov random field (MRF) theory, two-stage system implemented in CDMR, including first-stage optimal MRF...

The Deflate compression algorithm provides one of the most widely used solutions for lossless data compression. Field-programmable gate arrays (FPGAs) are commonly to implement hardware accelerators that speed up computation-intensive applications. In this article, FPGA-based and decompression described. These were specified in C++ synthesized using Vivado High-Level Synthesis (HLS) a Xilinx Virtex UltraScale+ series FPGA system clock frequency 250 MHz. proposed compressor processes at fixed...

This paper describes a synthesizable, transparent, built-in self-test (BIST) scheme for random-access memories (RAMs). By altering only two parameters in VHDL specification, BIST circuits can be automatically generated to detect 2-, 3- or 4-cell write-triggered coupling faults as well different classes of 5-cell faults. The represent either unlinked scrambled active physical neighborhood pattern-sensitive (PNPSFs), arbitrary combinations active, static, and passive PNPSFs. uses modified...

A stochastic sum-of-sinusoids based simulation model is proposed for Rayleigh and Rician fading channels. The time-averaged statistical properties of the new have been significantly improved compared to existing models. Verification simulator carried out by comparing its measured with ideal reference utilizes a time-overlapped implementation strategy provide compact design suitable multiple antenna simulators. An resulting on Xilinx Virtex-II Pro XC2VP100- 6 FPGA uses only 2% configurable...

We present an ultracompact and fast hardware simulator for Rayleigh Rician fading channels. To ensure numerical robustness efficient mapping onto hardware, the uses sum-of-sinusoids technique with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> = 32 sinusoids added up to model each path. Fading samples are generated at a low rate then passed interpolator, which computes final desired baseband rate. propose new time-multiplexed datapath that...

Taking advantage of the error resilience in many applications as well perceptual limitations humans, numerous approximate arithmetic circuits have been proposed that trade off accuracy for higher speed or lower power emerging exploit computing. However, characterizing various designs a specific application under certain performance constraints becomes new challenge. In this paper, adders and multipliers are evaluated compared better understanding their characteristics when implementations...

We propose two approximate leading one detector (LOD) designs and an adder (for summing logarithms) that can be used to improve the hardware efficiency of Mitchell logarithmic multiplier. The first LOD design uses a single fixed value `d' least significant bits (LSBs). For d=16 this reduces cost by 19.91% compared conventional 32-bit multiplier 15.19% when recent in literature. Our is smaller 32.33% more energy-efficient 56.77% with respect design. second partitions into fields increases...

This brief presents a novel computationally efficient design and implementation of Rayleigh flat fading-channel simulator. To generate complex Gaussian variates with the required U-shaped power spectrum, simulator utilizes an infinite-impulse response (IIR) spectrum shaping filter followed by multistage interpolators low-pass IIR filters. The new significantly simplifies characterization wireless systems providing fast area-efficient field-programmable gate array (FPGA) fading channel. Our...