A5009718624- Network Packet Processing and Optimization
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Caching and Content Delivery
- Semiconductor materials and devices
- VLSI and FPGA Design Techniques
- Video Coding and Compression Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Digital Filter Design and Implementation
- Magnetic properties of thin films
- Analog and Mixed-Signal Circuit Design
- Advanced Data Storage Technologies
- Radiation Effects in Electronics
- Low-power high-performance VLSI design
- Advancements in PLL and VCO Technologies
Gorgias Press (United States)
2014
University of Toronto
2003-2006
We survey recent developments in the design of large-capacity content-addressable memory (CAM). A CAM is a that implements lookup-table function single clock cycle using dedicated comparison circuitry. CAMs are especially popular network routers for packet forwarding and classification, but they also beneficial variety other applications require high-speed table lookup. The main CAM-design challenge to reduce power consumption associated with large amount parallel active circuitry, without...
This paper presents two techniques to reduce power consumption in content-addressable memories (CAMs). The first technique is pipeline the search operation by breaking match-lines into several segments. Since most stored words fail match their segments, discontinued for subsequent hence reducing power. second broadcast small-swing data on less capacitive global search-lines, and only amplify this signal full swing a shorter local search-line. As few match-line segments are active,...
Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These events, also referred as single-event upsets (SEUs), will become more problematic in future technologies. This paper presents a binary content-addressable memory (CAM) design with high immunity SEUs. Conventionally, error-correcting codes (ECC) have been used SRAMs address this issue, but these techniques not...
This paper presents a pipelined match-line and hierarchical search-line architecture to reduce power in content-addressable memories (CAM). The overall reduction is 60%, with 29% contributed by the match-lines 31% search-lines. proposed employed design of 1024/spl times/144 bit ternary CAM, achieving 7 ns search cycle time at 2.89 fJ/bit/search 0.18 /spl mu/m CMOS process.
We propose using caching to save power in content-addressable memories (CAMs). By a small cache along with the CAM, we avoid accessing larger and higher CAM. For hit rate of 90%, cache-CAM (C-CAM) saves 80% over conventional for cost 15% increase silicon area. Even at low 50%, savings 40% is achieved. The proposed C-CAM employed design testchip demonstrating 2.6 fJ/bit/search 0.18 mum CMOS process
Quick and accurate prediction of area, speed, power IP cores for SoC implementations reduces the design time thus overall cost. Accurate performance estimation early in cycle also is valuable identifying trade-offs different blocks that make up an SoC. This work provides empirical method IFFT/FFT multicarrier (OFDM, DMT) systems. The relative accuracy predictions allows comparison implementation alternatives, absolute enables final fabricated cores. methodology was verified through...
This paper presents four-valued magnetoresistive RAM (MRAM) storage cells using one access transistor and two binary magnetic tunnel junction (MTJ) devices, with the MTJ devices either in series or parallel. We present a comparative study of terms their area power benefits over MRAM, all same conventional MRAM process.