A5058751476- Parallel Computing and Optimization Techniques
- Security and Verification in Computing
- Interconnection Networks and Systems
- Embedded Systems Design Techniques
- Advanced Memory and Neural Computing
- Semiconductor materials and devices
- Radiation Effects in Electronics
- Advancements in Semiconductor Devices and Circuit Design
- Analog and Mixed-Signal Circuit Design
- Physical Unclonable Functions (PUFs) and Hardware Security
- CCD and CMOS Imaging Sensors
- Cryptographic Implementations and Security
- Low-power high-performance VLSI design
- UAV Applications and Optimization
- Distributed and Parallel Computing Systems
- VLSI and Analog Circuit Testing
- Advanced Data Storage Technologies
- Robotics and Sensor-Based Localization
- Distributed systems and fault tolerance
- Internet Traffic Analysis and Secure E-voting
- Advanced Malware Detection Techniques
- Advanced Neural Network Applications
- Real-time simulation and control systems
- Real-Time Systems Scheduling
ETH Zurich
2020-2025
University of Bologna
2023-2024
Technology Innovation Institute
2024
Vector architectures are gaining traction for highly efficient processing of data-parallel workloads, driven by all major ISAs (RISC-V, Arm, Intel), and boosted landmark chips, like the Arm SVE-based Fujitsu A64FX, powering TOP500 leader Fugaku. The RISC-V V extension has recently reached 1.0-Frozen status. Here, we present its first open-source implementation, discuss new specification's impact on micro-architecture a lane-based design, provide insights performance-oriented design coupled...
Open-source projects require outreach material to grow their community, secure funds, and strengthen influence. Numbers, specifications, facts alone are intangible uninvolved people; using a clear brand appealing visual is thus ample reach broad audience. This especially true for application-specific integrated circuits (ASICs) during the early stages of development cycle without running prototype systems. work presents ArtistIC, an open-source framework ASICs with top-metal art render GDSII...
The rapid advancement of energy-efficient parallel ultra-low-power (ULP) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> controllers units (MCUs) is enabling the development autonomous nano-sized unmanned aerial vehicles (nano-UAVs). These sub-10cm drones represent next generation unobtrusive robotic helpers and ubiquitous smart sensors. However, nano-UAVs face significant...
Microarchitectural timing channels enable unwanted information flow across security boundaries, violating fundamental assumptions.They leverage variations of several state-holding microarchitectural components and have been demonstrated instruction set architectures hardware implementations.Analogously to memory protection, Ge et al. [1] proposed time protection for preventing leakage via channels.They also showed that calls support.This work leverages the open extensible RISC-V architecture...
With the shrinking of technology nodes and use parallel processor clusters in hostile critical environments, such as space, run-time faults caused by radiation are a serious cross-cutting concern, also impacting architectural design. This paper introduces an approach to configurable soft-error tolerance at core level, augmenting six-core open-source RISC-V cluster with novel On-Demand Redundancy Grouping (ODRG) scheme. ODRG allows operate either two fault-tolerant cores, or six individual...
Microarchitectural timing channels use variations in the of events, resulting from competition for limited hardware resources, to leak information violation operating system's security policy. Such also exist on a simple in-order RISC-V core, as we demonstrate open-source RV64GC Ariane core. Time protection, recently proposed and implemented seL4 microkernel, aims prevent channels, but depends controlled reset microarchitectural state. Using Ariane, show that software techniques performing...
Covert channels enable information leakage across security boundaries of the operating system. Microarchitectural covert exploit changes in execution timing resulting from competing access to limited hardware resources. We use recent experimental support for time protection, aimed at preventing channels, seL4 microkernel and evaluate efficacy mechanisms against five known on Ariane, an open-source 64-bit application-class RISC-V core. confirm that without support, these defences are...
The complexity of automotive systems is increasing quickly due to the integration novel functionalities such as assisted or autonomous driving. However, poses considerable challenges supply chain since continuous addition new hardware and network cabling not considered tenable. availability modern heterogeneous multi-processor chips represents a unique opportunity reduce vehicle costs by integrating multiple into fewer Electronic Control Units (ECUs). In addition, recent improvements in...
Open Source Hardware, the way it should be!
Covert channels enable information leakage between security domains that should be isolated by observing execution differences in shared hardware. These can appear any stateful resource, including caches, predictors, and accelerators. Previous works have identified many vulnerable components, demonstrating defending against attacks via reverse engineering. However, this approach requires much human effort reasoning. With the Cambrian explosion of specialized hardware, it is becoming...
The rapid advancement of energy-efficient parallel ultra-low-power (ULP) ucontrollers units (MCUs) is enabling the development autonomous nano-sized unmanned aerial vehicles (nano-UAVs). These sub-10cm drones represent next generation unobtrusive robotic helpers and ubiquitous smart sensors. However, nano-UAVs face significant power payload constraints while requiring advanced computing capabilities akin to standard drones, including real-time Machine Learning (ML) performance safe...
We present Occamy, a 432-core RISC-V dual-chiplet 2.5D system for efficient sparse linear algebra and stencil computations on FP64 narrow (32-, 16-, 8-bit) SIMD FP data. Occamy features 48 clusters of cores with custom extensions, two 64-bit host cores, latency-tolerant multi-chiplet interconnect memory 32 GiB HBM2E. It achieves leading-edge utilization stencils (83 %), sparse-dense (42 sparse-sparse (49 %) matrix multiply.
Symmetric Multi-Processing (SMP) based on cache coherency is crucial for high-end embedded systems like automotive applications. RISC-V gaining traction, and open-source hardware (OSH) platforms offer solutions to issues such as IP costs vendor dependency. Existing multi-core cache-coherent are complex not efficient small core clusters. We propose an SystemVerilog implementation of a lightweight snoop-based cluster Linux-capable CVA6 cores. Our design uses the MOESI protocol via Arm's AMBA...
The widespread diffusion of compute-intensive edge-AI workloads and the stringent demands modern autonomous systems require advanced heterogeneous embedded architectures. Such architectures must support high-performance reliable execution parallel tasks with different levels criticality. Hardware-assisted virtualization is crucial for isolating applications concurrently executing these under real-time constraints, but interrupt poses challenges in ensuring transparency to virtual guests...
Microarchitectural timing channels exploit information leakage between security domains that should be isolated, bypassing the operating system's boundaries. These result from contention for shared microarchitectural state. In RISC-V instruction set, temporal fence (fence.t) was proposed to close by providing an system with means temporally partition state inexpensively in simple in-order cores. This work explores challenges fence.t superscalar out-of-order cores featuring large and...
Microarchitectural timing channels are a major threat to computer security. A set of OS mechanisms called time protection was recently proposed as principled way preventing information leakage through such and prototyped in the seL4 microkernel. We formalise underlying hardware that allows linking them information-flow proofs showed absence storage seL4.
Microarchitectural timing channels enable unwanted information flow across security boundaries, violating fundamental assumptions. They leverage variations of several state-holding microarchitectural components and have been demonstrated instruction set architectures hardware implementations. Analogously to memory protection, Ge et al. proposed time protection for preventing leakage via channels. also showed that calls support. This work leverages the open extensible RISC-V architecture...
With the shrinking of technology nodes and use parallel processor clusters in hostile critical environments, such as space, run-time faults caused by radiation are a serious cross-cutting concern, also impacting architectural design. This paper introduces an approach to configurable soft-error tolerance at core level, augmenting six-core open-source RISC-V cluster with novel On-Demand Redundancy Grouping (ODRG) scheme. ODRG allows operate either two fault-tolerant cores, or six individual...
Vector architectures are gaining traction for highly efficient processing of data-parallel workloads, driven by all major ISAs (RISC-V, Arm, Intel), and boosted landmark chips, like the Arm SVE-based Fujitsu A64FX, powering TOP500 leader Fugaku. The RISC-V V extension has recently reached 1.0-Frozen status. Here, we present its first open-source implementation, discuss new specification's impact on micro-architecture a lane-based design, provide insights performance-oriented design coupled...