This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in single word and enhance soft error immunity by employing Error Checking Correction (ECC) technique. proposed is demonstrated 72 Kb macro Negative Bit-Line (NBL) Write-assist an adaptive Read operation timing tracing circuit implemented 65 nm low-leakage CMOS...

In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write (WM), operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit test chip is implemented in 90 nm CMOS technology. The measurement results show that at 0.2 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , an frequency 6.0 MHz can be...

This paper presents a new bit-interleaving 12T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates architecture that can reduce multiple-bit errors in single word and enhance soft error immunity by employing checking correction (ECC) techniques. proposed is demonstrated 4 kb macro implemented 40 general purpose...

An LDPC decoder chip fully compliant to IEEE 802.16e applications is presented. Since the parity check matrix can be decomposed into sub-matrices which are either a zero-matrix or cyclic shifted matrix, phase-overlapping message passing scheme applied update messages immediately, leading enhance decoding throughput. With only one shifter-based permutation structure, self-routing switch network proposed merge 19 different sub-matrix sizes as defined in and enable parallel routed without...

In this paper, a detection and estimation scheme its architecture design for synchronization in 60 GHz indoor wireless transmission are presented. With the complementary Golay sequence based preamble structure, proposed is designed to detect symbol boundary, estimate frequency offset within unified architecture. For very high sampling speed at transmission, as 8 ×-parallelism with feed-forward data path. This supports single carrier (SC) orthogonal frequency-division multiplexing (OFDM)...

An LDPC codec chip supporting four code rates of IEEE 802.15.3c applications is presented. After utilizing row-based layered scheduling, the normalized min-sum (NMS) algorithm can reduce half iteration number while maintaining similar performance. According to unique structure parity-check matrix, a reconfigurable 8/16/32-input sorter designed deal with codes in different rates. Both input reallocation and pre-coded routing switch are proposed alleviate complexity, leading 64% reduction...

A low-error reduced-width Booth multiplier using a proper compensation vector is proposed. The dependent on the input data. value will thus be adaptively adjusted when data are different. Design results from 16/spl times/16 to 16 show that gate counts and critical path delay of new multipliers 50.94% 66.04% post-truncation multiplier. module generator our proposed architecture developed generate C code Verilog for each Pulse-shaping filter-system applications used in CATV transceivers...

This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the consists of memory groups, where each group has P banks. For consideration achieving both low delay time and area complexity, novel write/read scheduling mechanism is devised, so that outputs can be stored in those banks an optimized way. The proposed write current successively generated output data samples locations without any right after they are...

This paper presents a cross-point 512 kb 8 T pipeline static random-access memory (SRAM). The structure eliminates write half-select disturb to facilitate bit-interleaving architecture for enhanced soft error immunity. design employs boosted word-line (WL) improving both read performance and write-ability. A ripple bit-line (RiBL) provides 30%–44% access improvement 2 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex...

This brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write (WBL) cross-point data-aware structure to facilitate robust operation bit-interleaving architecture for enhanced soft error immunity. The design employs variation-tolerant line-up write-assist scheme where the timing of areaefficient boosted wordline negative WBL are aligned triggered/initiated by same low-going global maximize write-ability...

In this paper, a digital time domain equalizer (TDE) for 60 GHz radio frequency transmission systems is presented. Significantly, the TDE supports both single carrier (SC) and orthogonal frequency-division multiplexing (OFDM) operation modes baseband receiver. order to improve performance, proposed adopts Golay sequence aided one-shot channel estimation modified multi-path interference cancellation (MPIC) equalization. Targeting on line-of-sight (LOS) characteristic, MPIC simplified with...

A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing (SRN) features, messages are routed parallel fully support those specific 19 and 3 submatrix sizes defined IEEE 802.16e 802.11n applications with less hardware complexity. 6.22- mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> QC-LDPC...

In this paper, an 8X-parallelism all-digital baseband receiver is proposed to support SC and OFDM modes for both IEEE 802.15.3c 802.11ad standards. The contains a 4-in-1 synchronization (SYNC), 512-point radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> IFFT/FFT, phase noise cancellation (PNC), shared memory (MEM) bank frequency-domain equalizer (FDE) with optimized golay-correlator window-based (OGC-WNC) channel estimation (CE)...

This paper proposes a well-structured modified Booth encoding (MBE) multiplier architecture. The design adopts an improved encoder and selector to achieve extra-row-removal hybrid spare-tree approach two's complementation circuit both reduce the area improve speed. Experimental results on 32 bit show that it obtains power savings of 15.8% 11.7% respectively over classical 7.5% 5.5% best performance reported so far.

This article presents a high-throughput and low-routing complexity low-density parity check (LDPC) decoder design based on novel second minimum approximation min-sum (SAMS) algorithm. The routing congestion is mitigated by reducing the required interconnections in critical path of network. implementation postlayout results with 28-nm 1P9M CMOS process show that proposed can achieve throughput 10.5 Gb/s for millimeter-wave 60-GHz baseband system while satisfying low bit error rate (BER)...

This paper presents a new 8T SRAM cell with data-aware cross-point Write operation and series connected Read buffer for low power voltage operation. The features shared footer device to control the VGND pass-gate (Write) transistors buffer. row-based column-based Word-Line form structure, thus eliminating Half-Select Disturb facilitate bit-interleaving architecture. Replica based timing tracking circuit is used pulse width of Enable (WLE) signal overcome large variation at reduce active...

This paper proposes a novel algorithm and architecture for the adaptive feedback cancellation (AFC) based on pitch formant information hearing aid (HA) applications. The proposed method, named as Pitch Formant Estimation (PFE-AFC), has significantly low complexity compared to Prediction Error Method AFC (PEM-AFC). PFE-AFC consists of forward backward path processing. processing includes estimator decorrelation filter coefficients update voice activity detector speech detection, which...

A low-jitter digitally controlled oscillator (DCO) with multiphase differential outputs and good linearity is presented. The DCO composed of four delay cells can achieve linear tuning over a wide frequency range. proposed fully cell comprises logic in standard library varactors. measured rms jitter pk-pk from 2.5-GHz carrier are 2.827 29 ps, respectively. power consumption 6 mW 1.2 V supply. An experimental prototype designed using 65-nm CMOS technology, the chip area 156 μm × 92 <sup...

This paper proposes a new pipelined full-adder circuit structure for the implementation of arithmetic modules. With both static and dynamic structures, it has advantages high operational speed, smallest transistor count, low power/speed ratio. The adder cell is then used to design 8/spl times/8-b multiplier-accumulator (MAC). In this MAC, special designed reduce latency. MAC fabricated in 0.8-/spl mu/m single-poly-double-metal CMOS process. post-layout simulation shows that 1-b full can work...

This paper presents a new bit-interleaving 11T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to mitigate the leakage and variation improve Write-ability in deep sub-100nm technology. Measurement results from 4 Kb test chip implemented 40 nm General Purpose (40GP) CMOS technology operates for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> down 0.32 (~0.69X of threshold voltage)...

This study developed a high accuracy dynamic error-compensation circuit for fixed-width Booth multipliers based on probability and computer simulation (PACS). PACS begins by generating several potential solutions both conditional expected probability, whereupon the of is verified using solution with highest selected. In addition to being highly accurate, proposed approach area-effective. used TSMC 0.18-μm CMOS fabricate 16-bit multiplier an operating frequency 100 MHz power consumption 6.7 mW.

Switching noise due to di/dt is becoming severe as technology states, resulting in a great need for noise-suppression techniques. Several techniques reduce the switching caused by output buffers CMOS chips are described. An ac/dc buffer design technique proposed that includes an innovative feedback mechanism and signal ringing while at same time maintains timing dc current requirement. Also, of adaptively separated simultaneous can increase number simultaneously outputs per V/sub DD/ GND...

A time-domain adaptive decision feedback equaliser (ADFE) for multi-gigabit wire-line 2-pulse amplitude modulation (PAM) communication systems is proposed. The throughput rate of a conventional ADFE limited by the loops in circuit. This investigation develops two methods breaking or virtually these loops. first method batch mode coefficient updating (BMCU), and second concurrent lookahead (CLA) method. Since are broken broken, pipeline and/or parallel can be applied to design...

In this paper, a robust channel estimator for high- mobility space-time block code-orthogonal frequency division multiplexing (STBC-OFDM) systems is proposed and applied in IEEE 802.16e systems. A high-performance two-stage estimation method adopted. The architecture reduces computational complexity effectively improves 85.2% of the hardware implementation. performances design have been demonstrated through simulation an STBC-OFDM system with two transmit antennas one receive antenna. At...