Wei Tong

ORCID: 0000-0002-8834-4953
Publications
Citations
Views
---
Saved
---
About
Contact & Profiles
Research Areas
  • Advanced Data Storage Technologies
  • Parallel Computing and Optimization Techniques
  • Advanced Memory and Neural Computing
  • Caching and Content Delivery
  • Ferroelectric and Negative Capacitance Devices
  • Cloud Computing and Resource Management
  • Interconnection Networks and Systems
  • Cellular Automata and Applications
  • Distributed and Parallel Computing Systems
  • Robotic Path Planning Algorithms
  • Semiconductor materials and devices
  • Advanced Sensor and Control Systems
  • Magnetic Bearings and Levitation Dynamics
  • Distributed systems and fault tolerance
  • Embedded Systems and FPGA Design
  • Simulation and Modeling Applications
  • Algorithms and Data Compression
  • Advanced Computational Techniques and Applications
  • 2D Materials and Applications
  • Peer-to-Peer Network Technologies
  • Inertial Sensor and Navigation
  • Graphene research and applications
  • Marine Bivalve and Aquaculture Studies
  • Advanced Algorithms and Applications
  • IoT and Edge/Fog Computing

Wuhan National Laboratory for Optoelectronics
2016-2025

Huazhong University of Science and Technology
2016-2025

Chinese Academy of Medical Sciences & Peking Union Medical College
2025

Beihang University
2003-2024

Southern Marine Science and Engineering Guangdong Laboratory (Guangzhou)
2022-2024

Hong Kong University of Science and Technology
2022-2024

University of Hong Kong
2022-2024

Hunan University
2022-2023

Union Hospital
2022

North China University of Science and Technology
2021

Van der Waals (vdW) metallic contacts have been demonstrated as a promising approach to reduce the contact resistance and minimize Fermi level pinning at interface of two-dimensional (2D) semiconductors. However, only limited number metals can be mechanically peeled laminated fabricate vdW contacts, required manual transfer process is not scalable. Here, we report wafer-scale universal metal integration strategy readily applicable wide range By utilizing thermally decomposable polymer buffer...

10.1038/s41467-023-36715-6 article EN cc-by Nature Communications 2023-02-23

The Zoned Namespace (ZNS) Solid State Drive (SSD) is a nascent form of storage device that offers novel prospects for the Log Structured Merge Tree (LSM-tree). ZNS exposes erase blocks in SSD as append-only zones, enabling LSM-tree to gain awareness physical layout data. Nevertheless, on SSDs necessitates Garbage Collection (GC) owing mismatch between gigantic zones and relatively small Sorted String Tables (SSTables). Through extensive experiments, we observe smaller zone size can reduce...

10.1145/3608476 article EN ACM Transactions on Architecture and Code Optimization 2023-07-10

Breast cancer is a highly prevalent tumor worldwide. Mitochondrial permeability transition (MPT)-driven necrosis novel type of cell death induced by mitochondrial membrane disruption. The roles MPT-driven in breast remain unclear. Gene expression and clinicopathologic features were extracted from Cancer Genome Atlas Expression Omnibus. We performed genome landscape analysis (MPTdn)-related genes, consensus clustering was conducted to construct MPTdn clusters. Next, risk model established...

10.1186/s40001-025-02370-4 article EN cc-by-nc-nd European journal of medical research 2025-02-18

Securing systems’ main memory is important for building trusted data centers. To ensure security, encryption and integrity verification techniques update the security metadata (e.g., counters trees) during writes. Existing studies are optimistic about effect of writes on system performance since they regard all as background operations. However, we show that updates significantly increase write latency. High-latency frequently fill up buffers in system, forcing to perform critical path. As a...

10.1145/3722111 article EN ACM Transactions on Architecture and Code Optimization 2025-03-07

10.1109/tcad.2025.3552674 article EN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2025-01-01

Flash Translation Layer (FTL) is one of the most important components SSD, whose main purpose to perform logical physical address translation in a way that suitable unique characteristics memory technology. The pure page-mapping FTL scheme, arguably best scheme due its ability map any page number (LPN) (PPN) minimize erase operations, cannot be practically deployed since it consumes prohibitively large RAM (SRAM or DRAM) space store table for an SSD moderate size. Alternatives FTL, such as...

10.1109/msst.2010.5496970 article EN 2010-05-01

To suppress unbalanced vibrations of low-speed rotors suspended by magnetic bearings, such as a magnetically flywheel, an autobalancing control method based on elimination synchronous force has been applied. But its precision may decrease for high-speed moment gyros. The reason is that the low-pass characteristic amplifier in bearing system causes errors elimination. Moreover, this increases with rotational speed. resolve problem, we propose scheme using adaptive feedforward compensation...

10.1177/1077546313479990 article EN Journal of Vibration and Control 2013-05-07

Two-dimensional (2D) semiconductors have generated considerable attention for high-performance electronics and optoelectronics. However, to date, it is still challenging mechanically exfoliate large-area continuous monolayers while retaining their intrinsic properties. Here, we report a simple dry exfoliation approach produce large-scale 2D by using Ag film as the peeling tape. Importantly, conducting layer could be converted into AgOx nanoparticles at low annealing temperature, directly...

10.1021/acsnano.3c11573 article EN ACS Nano 2023-12-28

Emerging Resistive Random Access Memory (ReRAM) is a promising candidate as the replacement for DRAM due to its low standby power, high density, scalability, and nonvolatility. By employing unique crossbar structure, ReRAM can be constructed with extremely density. However, faces some serious challenges in terms of performance, reliability, energy consumption. First, ReRAM’s structure causes an IR drop problem wire resistance sneak currents, which results nonuniform access latency banks...

10.1145/3195799 article EN ACM Transactions on Architecture and Code Optimization 2018-05-23

Emerging computational resistive memory is promising to overcome the challenges of scalability and energy efficiency that DRAM faces also break through wall bottleneck. However, cell-level array-level nonideal properties significantly degrade reliability, performance, accuracy, during access analog computation. Cell-level nonidealities include nonlinearity, asymmetry, variability. Array-level interconnect resistance, parasitic capacitance, sneak current. This review summarizes practical...

10.1145/3325067 article EN ACM Transactions on Design Automation of Electronic Systems 2019-06-20

Total hip arthroplasty (THA) causes a great medical burden globally, and the same-day discharge (SDD) method has previously been considered to be cost saving. However, standard cost-effectiveness analysis (CEA) in randomized controlled trial (RCT) is needed evaluated benefits of SDD when performing THA from perspective both economic clinical outcomes. Eighty-four participants undergoing primary were either group or inpatient group. Outcomes assessed by an independent orthopedist who was not...

10.3389/fpubh.2022.825727 article EN cc-by Frontiers in Public Health 2022-04-25

Precise gene expression reflects the molecular response of deep-sea organisms to their harsh living environments. However, changes in environmental factors during lifting samples from deep sea a research vessel can also affect expression. By using transcriptomic approach, we compared profiles onboard fixed with situ limpet Bathyacmaea lactea. Our results revealed that concomitant stress conventional sampling without RNA fixation greatly influenced Various biological activities, such as cell...

10.1016/j.isci.2022.104092 article EN cc-by-nc-nd iScience 2022-03-17

10.1007/s11432-023-3751-y article EN Science China Information Sciences 2023-05-18

Emerging Resistive Memory (ReRAM) is a promising candidate as the replacement for DRAM because of its low power consumption, high density and endurance. Due to unique crossbar structure, ReRAM can be constructed with very density. However, ReRAM's structure causes an IR drop problem which results in non-uniform access latency banks reduces reliability. Besides, reliability arrays are greatly influenced by data patterns involved write operation. In this paper, we propose performance efficient...

10.1145/3061639.3062191 article EN 2017-06-13

Byte-addressable non-volatile memory (NVM) is emerging as an alternative for main memory. Non-volatile (NVMM) systems are required to support atomic persistence and deal with the high overhead of programming NVM cells. To this end, recent studies propose hardware logging data encoding designs NVMM systems. However, prior incur either extra ordering constraints or redundant log data. Moreover, existing unaware characteristics data, resulting in writing unnecessary bits.In paper, we a...

10.1109/isca45697.2020.00057 article EN 2020-05-01

Resistive random access memory (RRAM) is promising to be used as high density storage-class by employing crossbar structure. However, the wire resistance in array causes IR drop problem, which makes nonuniformity of write latency throughout array. In large array, differs greatly even same row. Since a region determined its slowest write-unit, conventional group-by-row partition and addressing scheme suboptimal for improving overall performance RRAM. this work, we present DAWS, novel RRAM...

10.1109/iccd.2017.50 article EN 2017-11-01

Emerging Non-Volatile Memories (NVMs) such as Phase Change Memory (PCM) and Resistive RAM (RRAM) are promising to replace traditional DRAM technology. However, they suffer from limited write endurance high energy consumption. Encoding methods Flip-N-Write, FlipMin CAFO can reduce the bit flips of NVMs by exploiting additional capacity store tag bits encoding methods. The effects overhead bits. In this paper, we propose COE COmpress cacheline for Extending lifetime NVMs. exploits space saved...

10.23919/date.2018.8342271 article EN Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 2018-03-01

Analog arithmetic operations are the most fundamental mathematical used in image and signal processing as well artificial intelligence (AI). In-memory computing (IMC) offers a high performance energy-efficient paradigm. To date, in-memory analog with emerging nonvolatile devices usually implemented using discrete components, which limits scalability blocks large scale integration. Here, prototypical implementation of (summation, subtraction multiplication) is experimentally demonstrated,...

10.1002/advs.202202478 article EN Advanced Science 2022-07-10

Tencent, one of the biggest Internet companies in China, contains billions users and over 600-PB data, leverages thousands SSDs storage system to improve performance obtain energy savings. Existing commercial however fail meet needs ultra largescale applications due not matching service patterns. In order address this problem deliver high performance, we propose an application-aware software-defined SSD scheme for Tencent applications, called TSSD. TSSD explores exploits business...

10.1109/icpads.2016.0071 article EN 2016-12-01

Resistive cross-point memory arrays can be used to construct high-density storage-class memory. However, coupled IR drop and sneak currents cause multidimensional non-uniformity of cell effective voltage in arrays. The significantly degrades write performance on if only adopting the worst-case latency at partial dimensions. Furthermore, depends dynamic operation parameters: row, column as well layer address, number selected cells, half-selected low-resistance state cells. In this article, we...

10.1109/tc.2020.2990884 article EN IEEE Transactions on Computers 2020-04-27

Zoned Namespace Solid State Drives (ZNS SSDs) delegate the data placement and garbage collection (GC) to host It can provide predictable performance, stable bandwidth for Log-Structured Merge Tree (LSMT) based key-value (KV) stores. We observe redundant migration in GC LSMT compaction, which exacerbates write amplification (WA) of KV store. In this paper, we propose our ZNS SSD store ZNSKV reduce by two major components. First, design Compaction-GC scheme completing part compaction. Second,...

10.1109/iccd56317.2022.00067 article EN 2022 IEEE 40th International Conference on Computer Design (ICCD) 2022-10-01

10.1109/asp-dac58780.2024.10473849 article EN 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) 2024-01-22
Coming Soon ...