A5059285190- Advanced Wireless Communication Techniques
- Error Correcting Code Techniques
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Interconnection Networks and Systems
- Low-power high-performance VLSI design
- Cooperative Communication and Network Coding
- Coding theory and cryptography
- VLSI and Analog Circuit Testing
- Radiation Effects in Electronics
- Advanced Memory and Neural Computing
- Semiconductor materials and devices
- Advanced Data Storage Technologies
- Ferroelectric and Negative Capacitance Devices
- Advanced Neural Network Applications
- Radio Frequency Integrated Circuit Design
- Optical Network Technologies
- Wireless Communication Networks Research
- VLSI and FPGA Design Techniques
- Algorithms and Data Compression
- Cellular Automata and Applications
- Numerical Methods and Algorithms
- Stochastic processes and financial applications
- 3D IC and TSV technologies
- Blind Source Separation Techniques
University of Kaiserslautern
2016-2025
Rheinland-Pfälzische Technische Universität Kaiserslautern-Landau
2013-2025
University of Koblenz and Landau
2023-2024
Kaiser (Czechia)
2023
University of Messina
2022
Agricultural Research Center
2022
Benha University
2022
Zagazig University
2022
South Valley University
2022
New Valley University
2022
Reliability concerns due to technology scaling have been a major focus of researchers and designers for several nodes. Therefore, many new techniques enhancing optimizing reliability emerged particularly within the last five ten years. This perspective paper introduces most prominent from today's points view roughly recapitulates progress in community so far. The this is on trends industrial as well academic that suggest way coping with challenges upcoming
This paper presents an efficient crossbar design and implementation intended for analog compute-in-memory (ACiM) acceleration of artificial neural networks based on ferroelectric FET (FeFET) technology. The novel mixed signal blocks presented in this work reduce the device-to-device variation are optimized low area, power high throughput. In addition, we illustrate operation programmability that adopts bit decomposition techniques MAC operation. Our ACiM accelerator achieves a record peak...
Advancements in AI led to the emergence of in-memory-computing architectures as a promising solution for associated computing and memory challenges. This study introduces novel (IMC) crossbar macro utilizing multi-level ferroelectric field-effect transistor (FeFET) cell multi-bit multiply accumulate (MAC) operations. The proposed 1FeFET-1R design stores information while minimizing device variability effects on accuracy. Experimental validation was performed using 28 nm HKMG technology-based...
A MIMO 3GPP-LTE digital baseband chip based on a heterogeneous 3 × 5 array NoC using 3.2 GOPS/50 mW programmable VLIW cores is presented. It features less than 10 ¿s run-time full physical layer reconfiguration and distributed power management leading to 477 consumption 4 2 RX application.
The paper presents an overview of a major research project on dependable embedded systems that has started in Fall 2010 and is running for projected duration six years. Aim 'dependability co-design' spans various levels abstraction the design process starting from gate level through operating system, applications software to system architecture. In addition, we present new classification faults, errors, failures.
Manufacturing-time process (P) variations and run-time voltage (V) temperature (T) can affect a DRAM's performance severely. To counter these effects, DRAM vendors provide substantial design-time PVT timing margins to guarantee correct functionality under worst-case operating conditions. Unfortunately, with technology scaling have become large very pessimistic for majority of the manufactured DRAMs. While are specific conditions as result, their difficult optimize, manufacturing-time effects...
In modern communication systems the required data rates are continuously increasing. High speed transmissions can easily generate throughputs far beyond 1 Tbit/s. To ensure error free communication, channel codes like Low-Density Parity Check (LDPC) utilized. However state-of-the-art LDPC decoders process only in range of 10 to 50 Gbit/s. This results a gap decoder performance which has be closed. Therefore we propose new ultra high architecture. We show that our architecture significantly...
Guaranteed numerical precision of each elementary step in a complex computation has been the mainstay traditional computing systems for many years. This era, fueled by Moore's law and constant exponential improvement efficiency, is at its twilight: from tiny nodes Internet-of-Things, to large HPC centers, sub-picoJoule/operation energy efficiency essential practical realizations. To overcome power wall, shift paradigms now mandatory. In this paper we present driving motivations, roadmap,...
We demonstrate that a cheap (30USD) small, low power 8x8 thermal sensor array can by itself provide broad range of information relevant for human activity monitoring in home and office environments. In particular the track people with an accuracy 1m (which is sufficient to recognize regions), detect operation mode various appliances such as toaster, water cooker or egg actions opening refrigerator, oven taking shower. While there are sensing modalities each above types (e.g. current sensors...
It is well known that many types of artificial neural networks, including recurrent can achieve a high classification accuracy even with low-precision weights and activations. The reduction in precision generally yields much more efficient hardware implementations regards to cost, memory requirements, energy, achievable throughput. In this paper, we present the first systematic exploration design space as function for Bidirectional Long Short-Term Memory (BiLSTM) network. Specifically,...
Theoretically, it is necessary to estimate the SNR when using a MAP of log-MAP constituent decoder. The effect an mismatch on bit error rate performance turbo-codes and design good variance estimators have been addressed by several authors. In this letter we study sensitivity turbo-decoding with max-log-MAP decoders respectively for AWGN Rayleigh fading channels. Our theoretical simulation results indicate that estimation not from practical point view. setup aligned decoder implementation...
The new standard for digital video broadcast DVB-S2 features low-density parity-check (LDPC) codes as their channel coding scheme. are defined various code rates with a block size of 64800 which allows transmission close to the theoretical limits. decoding LDPC is an iterative process. For about 300000 messages processed and reordered in each 30 iterations. These huge data processing storage requirements real challenge decoder hardware realization, has fulfill specified throughput 255 Mbit/s...
The upcoming IEEE WiMax 802.16e standard, also referred to as WirelessMAN (2005), is the next step toward very high throughput wireless backbone architectures, supporting up 500 Mbps. It features an advanced channel coding scheme low-density parity-check codes. decoding of LDPC codes iterative process, hence many data have be exchanged between processing units within each iteration. variety specified and envision different schedules for pose significant challenges decoder hardware...
3GPP long term evolution (LTE) enhances the wireless communication standards UMTS and HSDPA towards higher throughput. A throughput of 150 Mbit/s is specified for LTE using 2×2 MIMO. For this, highly punctured Turbo codes with rates up to 0.95 are used channel coding, which a big challenge decoder design. This paper investigates efficient architectures codes. We present code decoder, part an industrial SDR multi-standard baseband processor chip.
Cooperation of CPU and hardware accelerator to accomplish computational intensive tasks, provides significant advantages in run-time speed energy. Efficient management data sharing among multiple kernels can rapidly turn into a complicated problem. The Accelerator coherency port (ACP) emerges as possible solution by enabling accelerators issue coherent accesses the memory space. In this paper, we quantify using ACP over traditional method on DRAM. We select Xilinx ZYNQ target develop an...
3D integration based on TSV (through silicon via) technology enables stacking of multiple memory layers and has the advantage higher bandwidth at lower energy consumption for interface. As in mobile applications efficiency is key, especially here a strategic technology. In this paper we focus design space exploration 3D-stacked DRAMs with respect to performance, area densities from 256Mbit 4Gbit per 3D-DRAM channel. We investigate four different nodes 75nm down 45nm show optimal point...
In systems ranging from mobile devices to servers, Dynamic Random Access Memories (DRAM) have a big impact on performance and contributes significant part of the total consumed power. Conventional DDR3-based solutions are stretched thin as their maximum bandwidth is limited by I/O count interface speed. As new coming onto market (JEDEC DDR4, JEDEC WIDE I/O, Micron's hybrid memory cube: HMC or JEDEC's high memory: HBM) it critical evaluate these assess suitability for specific applications....
Optical Character Recognition is conversion of printed or handwritten text images into machine-encoded text. It a building block many processes such as machine translation, text-to-speech and mining. Bidirectional Long Short-Term Memory Neural Networks have shown superior performance in character recognition with respect to other types neural networks. In this paper, the best our knowledge, we propose first hardware architecture Network Connectionist Temporal Classification for Recognition....
Recent progress in quantum computers severely endangers the security of widely used public-key cryptosystems and all communication that relies on it. Thus, US NIST is currently exploring new post-quantum cryptographic algorithms are robust against computers. Security seen as one most critical issues low-power IoT devices-even with pre-quantum cryptography-since devices have tight energy constraints, limited computational power strict memory limitations. In this paper, we present, to best our...
Spatially coupled serially concatenated codes (SC-SCCs) are constructed by coupling several classical turbo-like component codes. The resulting spatially provide a close-to-capacity performance and low error floor, which have attracted lot of interest in the past few years. aim this paper is to perform comprehensive design space exploration reveal different aspects SC-SCCs, missing literature. More specifically, we investigate effect block length, memory, decoding window size, number...
The advent of in-memory computing has introduced a new paradigm computation, which offers significant improvements in terms latency and power consumption for emerging embedded AI accelerators. Nevertheless, the effect hardware variations non-idealities memory technologies may significantly compromise accuracy inferred neural networks result malfunctions safety-critical applications. This article addresses issue from three different perspectives. First, we describe technology-related sources...
Wheat Stripe Rust Disease (WRD) poses a significant threat to wheat crops, causing substantial yield losses and can result in total crop damage if not detected early. The localization of WRD-infected areas is labor-intensive time-consuming task due the intricate varied nature disease spread, especially for large plantations. Hence, segmentation crops vital early identification WRD-affected area, which allows implementation targeted intervention measures. state-of-the-art technique WRD using...