Developed specifically to enable research in TCP/IP networking, the M5 simulator provides features necessary for simulating networked hosts, including full-system capability, a detailed I/O subsystem, and ability simulate multiple systems deterministically. M5's usefulness as general-purpose architecture its liberal open-source license have led adoption by several academic commercial groups.

Analysis of technology and application trends reveals a growing imbalance in the peak compute-to-memory-capacity ratio for future servers. At same time, fraction contributed by memory systems to total datacenter costs power consumption during typical usage is increasing. In response these trends, this paper re-examines traditional compute-memory co-location on single system details design new general-purpose architectural building block-a blade-that allows be "disaggregated" across ensemble....

We created a novel optical security device that integrates multiple computer-generated holograms within single colour image. Under white light, this "holographic print" appears as image, whereas illumination with red, green, or blue beam from handheld laser pointer projects up to three different onto distant screen. In our design, all dielectric layered pixels comprising phase plates (phase control) and structural filters (amplitude are tiled form monolithic print, wherein pixel-level...

This paper seeks to understand and design next-generation servers for emerging "warehouse-computing" environments. We make two key contributions. First, we put together a detailed evaluation infrastructure including new benchmark suite warehouse-computing workloads, performance, cost, power models, quantitatively characterize bottlenecks. Second, study solution that incorporates volume non-server-class components in novel packaging solutions, with memory sharing flash-based disk caching. Our...

The explosive growth in digital data and its growing role real-time decision support motivate the design of high-performance database management systems (DBMSs). Meanwhile, slowdown supply voltage scaling has stymied improvements core performance ushered an era power-limited chips. These developments DBMS accelerators that (a) maximize utility by accelerating dominant operations, (b) provide flexibility choice DBMS, layout, types.

Distributed in-memory key-value stores, such as memcached, are central to the scalability of modern internet services. Current deployments use commodity servers with high-end processors. However, given cost-sensitivity services and recent proliferation volume low-power System-on-Chip (SoC) designs, we see an opportunity for alternative architectures. We undertake a detailed characterization memcached reveal performance power inefficiencies. Our study considers both high-performance CPUs NICs...

Recent research on memory disaggregation introduces a new architectural building block — the blade as cost-effective approach for capacity expansion and sharing an ensemble of servers. Memory blades augment servers' local with second-level (remote) that can be dynamically apportioned among in response to changing demand, albeit at higher access latency. In this paper, we build prior explore software systems implications disaggregated memory. We develop software-based prototype by extending...

This paper seeks to understand and design next-generation servers for emerging "warehouse-computing" environments. We make two key contributions. First, we put together a detailed evaluation infrastructure including new benchmark suite warehouse-computing workloads, performance, cost, power models, quantitatively characterize bottlenecks. Second, study solution that incorporates volume non-server-class components in novel packaging solutions, with memory sharing flash-based disk caching. Our...

Abstract Interactive materials capable of changing appearance upon exposure to external stimuli, such as photonic inks, are generally difficult achieve on a large scale they often require self‐assembly processes that control macroscopically. Here this problem is overcome by preparing arrays cellulose nanocrystal (CNC) microfilms from discrete nanoliter sessile droplets. The obtained show extremely uniform and intense color, enabling exceptional consistency in optical across the entire array....

Analysis of technology and application trends reveals a growing imbalance in the peak compute-to-memory-capacity ratio for future servers. At same time, fraction contributed by memory systems to total datacenter costs power consumption during typical usage is increasing. In response these trends, this paper re-examines traditional compute-memory co-location on single system details design new general-purpose architectural building block-a blade-that allows be "disaggregated" across ensemble....

Providing low-latency access to large amounts of data is one the foremost requirements for many web services. To address these needs, systems such as Memcached have been created which provide a distributed, all in-memory key-value store. These are critical and often deployed across hundreds or thousands servers. However, not well matched commodity servers, they require significant CPU resources achieve reasonable network bandwidth, yet core functions do benefit from high performance standard...

Sculpting nanostructures into different geometries in either one or two dimensions produces a wide range of colorful elements microscopic prints. However, achieving shades gray and control color saturation remain challenging. Here, we report complete approach to grayscale generation based on the tuning single nanostructure geometry. Through two-photon polymerization lithography, systematically investigated from basic nanopillar geometry low-refractive-index (n < 1.6) material. Grayscale full...

A System-on-Chip (SoC) integrates multiple discrete components into a single chip, for example by placing CPU cores, network interfaces and I/O controllers on the same die. While SoCs have dominated high-end embedded products over decade, system-level integration is relatively new trend in servers, driven opportunity to lower cost (by reducing number of parts) power pin crossings from cores I/O). Today, mounting pressures scale-out dat-acenters demand technologies that can decrease Total...

Directing the self-assembly of sub-10-nm nanoparticles has been challenging because simultaneous requirements to achieve a densely packed monolayer and rearrange assemble within template. We met both by separating processes into two steps first forming gold on suitable liquid subphase anisole then transferring it edgewise onto silicon substrate with prepatterned template comprising nanoposts nanogratings. Doing so resulted in that assembled commensuration design while exhibiting appreciable...

A diffraction-limited three-dimensional (3D) direct laser writing (DLW) system based on two-photon polymerization can routinely pattern structures at the 100 nm length scale. Several schemes have been developed to improve patterning resolution of 3D DLW but often require customized resist formulations or multi-wavelength exposures. Here, we introduce a scheme produce suspended nano-webs with feature sizes below 10 in IP-Dip using sub-threshold exposure conditions commercial system. The...

Halide perovskites hold exceptional promise as cheap, low temperature solution-processed optoelectronic materials. Yet they are hindered by poor structural and chemical stability, rapidly degrading when exposed to moisture or air. We demonstrate a solution-phase method for infiltrating methylammonium lead bromide perovskite (CH3NH3PbBr3, MAPbBr3) into nanoporous GaN which preserved the green photoluminescence of after up 1 year storage under ambient conditions. Besides protective effect,...

Motivated by the challenges of scaling up memory capacity and fully exploiting benefits compression, we propose Buri, a hardware-based compression scheme, which simultaneously achieves cost efficiency, high performance, ease adoption. Buri combines (1) self-contained, ready-to-adopt hardware module, manages metadata allocation/relocation operations; (2) set optimization mechanisms, reduce area performance overheads in accommodating address indirection required compression; (3) lightweight...

We report on the directed self-assembly of sub-10 nm gold nanoparticles confined within a template comprising channels gradually varying widths. When colloidal lattice parameter is mismatched with channel width, rearrange and break their natural close-packed ordering, transiting through range structural configurations according to constraints imposed by channel. While much work has been done in assembling ordered configurations, studies transition regime between states have limited...

Distributed in-memory key-value stores, such as memcached, are central to the scalability of modern internet services. Current deployments use commodity servers with high-end processors. However, given cost-sensitivity services and recent proliferation volume low-power System-on-Chip (SoC) designs, we see an opportunity for alternative architectures. We undertake a detailed characterization memcached reveal performance power inefficiencies. Our study considers both high-performance CPUs NICs...

The adoption of non-volatile memories (NVMs) in system architecture and the growth data-centric workloads offer exciting opportunities for new designs. In this paper, we examine potential limit designs that move compute close proximity to NVM-based data stores. To address challenges evaluating such architectures distributed systems, develop validate a methodology large-scale workloads. We then study "nanostores" as an example design constructs systems from building blocks with 3D-stacked NVM...

The emergence of big data analytics and the need for cost/energy efficient IT infrastructure motivate a new focus on data-centric designs. In this paper, we aim to better understand design implications systems by quantifying workload requirements runtime dynamics. We examine four workloads representing trends fast decisions, total integration, deep analysis fresh insights: an archive store, columnar database enhanced with table compression, engine distributed R, transaction/analytics hybrid...

Priority queues are abstract data structures where each element is associated with a priority, and the highest priority always retrieved first from queue. The structure widely used within databases, including last stage of merge-sort, forecasting read-ahead I/O to stream for replacement selection sort. Typical software implementations use balanced binary tree-based structure, providing O(log N) time both enqueue dequeue operations. To improve performance, we propose several scalable...