Through-silicon-vias (TSVs) can potentially be used to implement inductors in 3-D integrated systems for minimal footprint and large inductance. However, different from conventional 2-D spiral inductors, TSV are fully buried the lossy substrate, thus suffering low quality factors. In this paper, we systematically examine how various process design parameters affect their performance. A few interesting phenomena that unique observed. We then propose a novel shield mechanism utilizing...

Amino acid identification is crucial across various scientific disciplines, including biochemistry, pharmaceutical research, and medical diagnostics. However, traditional methods such as mass spectrometry require extensive sample preparation are time-consuming, complex costly. Therefore, this study presents a pioneering Machine Learning (ML) approach for automatic amino by utilizing the unique absorption profiles from an Elliptical Dichroism (ED) spectrometer. Advanced data preprocessing...

There has been a tremendous research effort in recent years to move DC-DC converters on chip for enhanced performance. However, major limiting factor implementing on-chip inductive is the large area overhead induced by spiral inductors. Thus, we propose using through-silicon-vias (TSVs), critical enabling technique three-dimensional (3D) integrated systems, implement inductors converters. While existing literature show that TSV are inferior compared with conventional due substrate loss RF...

Through-silicon-vias (TSVs) can potentially be used to implement inductors in three-dimensional (3D) integrated systems for minimal footprint and large inductance. However, different from conventional 2D spiral inductors, TSV are fully buried the lossy substrate, thus suffering low quality factor. In this paper, we propose a novel shield mechanism utilizing micro-channel, technique conventionally heat removal, reduce substrate loss. This increases factor inductance of inductor by up 21x 17x...

<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> resonant clock is a viable option for low power on-chip distributions. A major limiting factor to its implementation the large area overhead due use of conventional spiral inductors. On other hand, idle through-silicon-vias (TSVs) in 3-D integrated circuits (3-D ICs) can form vertical inductors with minimal footprint and have little noise coupling horizontal traces, particularly suitable...

On-chip inductive buck converters gain popularity due to their higher efficiency at load currents compared its linear and capacitive counterparts. Through-silicon-via inductors (TSV-Inductors) in 3-D integrated circuit (3-D IC) technology can be used for the converter implementation that reduces metal resource consumption of inductor. However, ICs, regulated voltage from might required multiple tiers. Simply designing one per tier is apparently consuming. This paper fully utilizes feature...

Transistor-level monolithic three-dimensional integrated circuit (M3D-IC) technology potential is compromised with the silicon footprint overhead caused by metal inter-layer via (MIV). To address this issue, we present a dual-purpose MIV-device utilization where MIV serves two purposes: 1. interconnect and 2. device terminal. A detailed study of proposed MIV-devices specifically MIV-capacitor MIV-transistor performed strategy to extract level-3 Spice models presented in paper. Simulation...

LC resonant clock is an attracting option for low power on-chip distribution designs. However, a major limiting factor to its implementation the large area overhead due conventional spiral inductors. On other hand, idle through-silicon-vias (TSVs) in three-dimensional integrated circuits (3D ICs) can form vertical inductors with minimal footprint and little noise coupling horizontal traces, particularly suitable application of clock. strict constraints on location TSVs, use TSV inductor...

Metal inter-layer via (MIV) in Monolithic three-dimensional integrated circuits (M3D-IC) is used to connect devices and provide power clock signals across multiple layers. The size of MIV comparable logic gates because the significant reduction substrate layers due sequential integration. Despite MIV's small size, impact on performance adjacent should be considered implement IC designs M3D-IC technology. In this work, we systematically study changes transistors when they are placed near...

LC resonant clock is an attracting option for low power on-chip distribution designs. However, a major limiting factor to its implementation the large area overhead due conventional spiral inductors. On other hand, idle through-silicon-vias (TSVs) in three-dimensional integrated circuits (3D ICs) can form vertical inductors with minimal footprint and little noise coupling horizontal traces, particularly suitable application of clock. strict constraints on location TSVs, use TSV inductor...

Conventional on-chip spiral inductor consumes significant top metal routing area, thereby preventing its popularity in many applications. Recently TSV-inductor with a magnetic core has been proved to be viable option for DC-DC converter 14nm test chip. The operating conditions of such inductors play major role maximizing the performance and efficiency converter. However, due unique TSV-structure, unlike conventional inductor, much modeling details remain unclear. This paper analyzes proposes...

Through-silicon-vias (TSVs) are the enabling technique for three-dimensional integrated circuits (3D ICs). However, their large area significantly reduces benefits that can be obtained by 3D ICs. On other hand, a major limiting factor implementation of many on-chip such as DC-DC converters and resonant clocking is overhead induced spiral inductors. Several works have been proposed in literature to make inductors out idle TSVs. In this paper, we will demonstrate effectiveness TSV addressing...

Three-dimensional integrated circuit (3D-IC) technology gained prominence for future chips (ICs) due to increased transistor density at the same node. Conventional 3D-IC implementation involves die stacking with vertical interconnects realized by through-silicon-via (TSV). One of main challenges associated is TSV size since they are large in (100-400x larger than standard cells 45nm technology) and their diameters do not scale technology. In addition, lot dummy TSVs inserted satisfy minimum...

Monolithic three-dimensional integrated circuit (M3D-IC) technology can potentially improve transistor density, performance and power efficiency for future IC designs. To attain maximum benefits of M3D-IC technology, the silicon footprint overhead caused by metal inter-layer via (MIV) should be reduced because MIV passes through silicon. In this paper, we present dual-purpose utilization where serves two purposes: 1. interconnect 2. device terminal. The active devices that are formed using...

Monolithic Three-Dimensional Integrated Circuits (M3D-IC) has become an attractive option to increase the transistor density. In M3D-IC, substrate layers are realized on top of previous using sequential integration techniques. Recent works in M3D-IC have demonstrated feasibility FDSOI process-based implementations and, Metal inter-layer vias (MIVs) used provide connections between devices. Since MIVs extended from bottom layer layer, they occupy a small area resulting overhead. Additionally,...

There has been a tremendous research effort in recent years to move DC-DC converters on chip for enhanced performance. To reduce the large area overhead induced by conventional spiral inductors, existing literature used through-silicon-vias (TSVs) inductors basic without feedback control. In this paper, we further study possible application of TSV with Pulse Width Modulation (PWM)-controlled feedback. The converter inductor is at par terms performance other designs literature. Experimental...

The conventional on-chip spiral inductor consumes a significant top-metal routing area, thereby preventing its popularity in many applications. Recently through-silicon-via– (TSV) based (also known as TSV-inductor) with magnetic core has been proved to be viable option for the DC-DC converter. operating conditions of these inductors play major role maximizing performance and efficiency However, there is critical need study design optimization details TSV-inductors unique three-dimensional...

Due to heterogeneous integration, there is an increased demand for on-chip voltage regulators provide many domains efficient operation of the system. Towards this, planar magnetic-core based inductors gained popularity due their inductance density buck converter realization. To ensure proper converter, should not saturate, and over-design inductor decreases efficiency significantly. Also, area budget allocated implementation will be limited. This paper details design analysis solenoid...

Due to heterogeneous integration, there is an increased demand for on-chip DC-DC converters provide multiple voltage domains efficient operation of the system. Towards this, planar magnetic-core based inductors gained popularity due their inductance density buck converter realization. To ensure proper converter, should not saturate, and over-design inductor decreases efficiency significantly. Also, area budget limited design. This paper proposes optimization framework design multi-phase with...