A5075888890- Parallel Computing and Optimization Techniques
- Advanced Data Storage Technologies
- Auditing, Earnings Management, Governance
- Distributed systems and fault tolerance
- Interconnection Networks and Systems
- Accounting and Organizational Management
- Fungal Biology and Applications
- Accounting Education and Careers
- Distributed and Parallel Computing Systems
- Embedded Systems Design Techniques
- Corporate Finance and Governance
- Enzyme-mediated dye degradation
- Mycorrhizal Fungi and Plant Interactions
- Cardiac Valve Diseases and Treatments
- Cloud Computing and Resource Management
- Financial Reporting and Valuation Research
- Robotic Process Automation Applications
- Advanced Memory and Neural Computing
- Radiation Effects in Electronics
- Risk Management in Financial Firms
- Infective Endocarditis Diagnosis and Management
- Biofuel production and bioconversion
- Head and Neck Cancer Studies
- Enzyme Production and Characterization
- Ethics in Business and Education
Brigham Young University
2015-2024
University of British Columbia
2008-2024
Vancouver General Hospital
2018-2024
St. Paul's Hospital
2012-2024
EDF Energy (United Kingdom)
2015-2024
The University of Western Australia
2022
St. Paul's Hospital
2012-2022
Okanagan University College
2022
University of Wisconsin–Madison
2010-2021
Advanced Micro Devices (United States)
2013-2021
The gem5 simulation infrastructure is the merger of best aspects M5 [4] and GEMS [9] simulators. provides a highly configurable framework, multiple ISAs, diverse CPU models. complements these features with detailed exible memory system, including support for cache coherence protocols interconnect Currently, supports most commercial ISAs (ARM, ALPHA, MIPS, Power, SPARC, x86), booting Linux on three them x86). project result combined efforts many academic industrial institutions, AMD, ARM, HP,...
The Wisconsin Multifacet Project has created a simulation toolset to characterize and evaluate the performance of multiprocessor hardware systems commonly used as database web servers. We leverage an existing full-system functional infrastructure (Simics [14]) basis around which build set timing simulator modules for modeling memory system microprocessors. This enables us run architectural experiments using suite scaled-down commercial workloads [3]. To enable other researchers more easily...
With the availability of very large, relatively inexpensive main memories, it is becoming possible keep large databases resident in memory In this paper we consider changes necessary to permit a relational database system take advantage amounts We evaluate AVL vs B+-tree access methods for databases, hash-based query processing strategies sort-merge, and study recovery issues when most or all fits As expected, B+-trees are preferred storage mechanism unless more than 80--90% A somewhat...
Transactional memory (TM) simplifies parallel programming by guaranteeing that transactions appear to execute atomically and in isolation. Implementing these properties includes providing data version management for the simultaneous storage of both new (visible if transaction commits) old (retained aborts) values. Most (hardware) TM systems leave values "in place" (the target address) buffer elsewhere until commit. This makes aborts fast, but penalizes much more frequent) commits. In this...
ABSTRACT: Internal auditors perform work that is relevant to their host entities' financial reporting processes; yet, little research attention has focused on the effects of internal auditing companies' external reporting. Using a unique and previously unavailable data set, we investigate relation between audit function (IAF) quality earnings management. We measure IAF using composite comprising six individual components based SAS No. 65, which guides in assessing an with respect its role...
Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, programming languages. Today's machines limit these to a single communication paradigm, either message-passing or shared-memory, which results uneven performance. This paper addresses this problem by defining an interface, Tempest, that exposes low-level and memory-system mechanisms so programmers compilers can customize policies for given application. Typhoon is...
In response to increasing (relative) wire delay, architects have proposed various technologies manage the impact of slow wires on large uniprocessor L2 caches. Block migration (e.g., D-NUCA and NuRapid) reduces average hit latency by migrating frequently used blocks towards lower-latency banks. Transmission Line Caches (TLC) use on-chip transmission lines provide low all Traditional stride-based hardware prefetching strives tolerate, rather than reduce, latency. Chip multiprocessors (CMPs)...
Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware.
SYNOPSIS We investigate the implementation of Robotic Process Automation (RPA) software in public accounting by interviewing RPA leaders at Big 4 firms. automates input, processing, and output data to streamline repetitive, mundane tasks. Many our findings are unique accounting. For instance, participants report tax services furthest along adoption, followed advisory assurance services. Furthermore, has not impacted fees, but there is concern that clients may desire fee reductions due...
SUMMARY The overall complexity and estimation uncertainty inherent in financial statements have increased recent decades; however, the related reports services changed very little, including format of balance sheet income statement, content auditor's report, level nature assurance provided on estimates. We examine estimates reported by public companies find that fair value other based management's subjective models inputs contain or imprecision is many times greater than materiality....
gem5-gpu is a new simulator that models tightly integrated CPU-GPU systems. It builds on gem5, modular full-system CPU simulator, and GPGPUSim, detailed GPGPU simulator. routes most memory accesses through Ruby, which highly configurable system in gem5. By doing this, it able to simulate many configurations, ranging from with coherent caches single virtual address space across the GPU maintains separate physical spaces. gem5gpu can run unmodified CUDA 3.2 source code. Applications launch...
ABSTRACT: Academic literature and the business press have placed increased attention on corporate disclosure of nonfinancial information. This study uses a survey 750 retail investors to examine perceptions about indicators economic performance, governance policies social responsibility. Survey results indicate that currently are most concerned with performance information, followed by governance, then responsibility Those respondents who hold socially responsible investments use more all...
ABSTRACT ChatGPT, a language-learning model chatbot, has garnered considerable attention for its ability to respond users’ questions. Using data from 14 countries and 186 institutions, we compare ChatGPT student performance 28,085 questions accounting assessments textbook test banks. As of January 2023, provides correct answers 56.5 percent partially an additional 9.4 When considering point values questions, students significantly outperform with 76.7 average on compared 47.5 if no partial...
Abstract ChatGPT frequently appears in the media, with many predicting significant disruptions, especially fields of accounting and auditing. Yet research has demonstrated relatively poor performance on student assessment questions. We extend this to examine whether more recent models capabilities can pass major certification exams including Certified Public Accountant (CPA), Management (CMA), Internal Auditor (CIA), Enrolled Agent (EA) exams. find that 3.5 model cannot any exam (average...
We have developed a new technique for evaluating cache coherent, shared-memory computers. The Wisconsin Wind Tunnel (WWT) runs parallel program on computer (CM-5) and uses execution-driven, distributed, discrete-event simulation to accurately calculate execution time. WWT is virtual prototype that exploits similarities between the system under design (the target) an existing evaluation platform host). host directly executes all target instructions memory references hit in cache. WWT's shared...
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At abstract level, SafetyNet logically maintains multiple, globally consistent checkpoints of the state shared memory multiprocessor (i.e., processors, memory, and coherence permissions), it recovers pre-fault checkpoint system re-executes if is detected. efficiently coordinates across in logical time "logically...
Many future shared-memory multiprocessor servers will both target commercial workloads and use highly-integrated "glueless" designs. Implementing low-latency cache coherence in these systems is difficult, because traditional approaches either add indirection for common cache-to-cache misses (directory protocols) or require a totally-ordered interconnect (traditional snooping protocols). Unfortunately, interconnects are difficult to implement glueless An ideal protocol would avoid...
This paper discusses implementations of fine-grain memory access control, which selectively restricts reads and writes to cache-block-sized regions. Fine-grain control forms the basis efficient cache-coherent shared memory. focuses on low-cost that require little or no additional hardware. These techniques permit implementation a wide range parallel systems, thereby providing shared-memory codes with portability previously limited message passing.
article Implementing a cache consistency protocol Share on Authors: R. H. Katz Computer Science Division, Electrical Engineering and Department, University of California, Berkeley, CA CAView Profile , S. J. Eggers D. A. Wood C. L. Perkins G. Sheldon Authors Info & Claims ACM SIGARCH Architecture NewsVolume 13Issue 3June 1985 pp 276–283https://doi.org/10.1145/327070.327237Published:01 June 238citation1,099DownloadsMetricsTotal Citations238Total Downloads1,099Last 12 Months24Last 6 weeks4 Get...
Modern processors use two or more levels ofcache memories to bridge the rising disparity betweenprocessor and memory speeds. Compression canimprove cache performance by increasing effectivecache capacity eliminating misses. However,decompressing lines also increases accesslatency, potentially degrading performance.In this paper, we develop an adaptive policy thatdynamically adapts costs benefits of cachecompression. We propose a two-level hierarchywhere L1 holds uncompressed data L2cache...