A secure reset operation could be an enabling technology that allows sharing of a quantum computer among different users, or programs the same user. Today, dominant method to erase qubit state is full system wipe, which effectively resets all qubits at time. In today's superconducting machines from IBM, for example, wipe takes up 1000 μs, and it fully erases information in system. However, with there no means only few cleared assigned new user program; everything has erased allow resetting...

Caches are one of the key features modern processors as they help to improve memory access timing through caching recently used data. However, due differences between cache hits and misses, numerous side-channels have been discovered exploited in past. In this paper, Computation Tree Logic is model execution paths processor logic, derive formulas for that can lead side-channel vulnerabilities. total, 28 types attacks presented: 20 which map previously categorized or discussed literature, 8...

This paper focuses on a new attack vector in modern processors: the timing-based side and covert channel attacks due to Translation Look-aside Buffers (TLBs). first presents novel three-step modeling approach that is used exhaustively enumerate all possible TLB vulnerabilities. Building model, this then shows how automatically generate micro security benchmarks test for After showing insecurity of standard TLBs, two secure designs are presented: Static-Partition (SP) Random-Fill (RF) TLB....

This paper evaluates new security threats due to the processor frontend in modern Intel processors. The root causes of are multiple paths that micro-operations can take: through Micro-Instruction Translation Engine (MITE), Decode Stream Buffer (DSB), also called Micro-operation Cache, or Loop Detector (LSD). Each path has its own unique timing and power signatures, which lead side- covert-channel attacks presented this work. Especially, switching between different leads observable...

Based on improvements to an existing three-step model for cache timing-based attacks, this work presents 88 Strong types of theoretical vulnerabilities in processor caches. It also and implements a new benchmark suite that can be used test if is vulnerable one the attacks. In total, there are 1094 automatically-generated programs which cover vulnerabilities. The generates Cache Timing Vulnerability Score (CTVS) evaluate how specific implementation different A smaller CTVS means design more...

This work presents a design-time security verification framework for secure processor architectures. Our new SecChisel is built upon the Chisel hardware construction language and tools, uses information flow analysis to verify properties of an architecture at design-time. To enforce security, supports adding tags wires, registers, modules, other parts design description, as well allows defining custom lattice policies. The performs automatic tag propagation in parser checking using Z3 SMT...

Timing-based side and covert channels in processor caches continue to be a threat modern computers. This work shows for the first time, systematic, large-scale analysis of Arm devices detailed results attacks processors are vulnerable to. Compared x86, uses different architectures, microarchitectural implementations, cache replacement policies, etc., which affects how can launched, security testing vulnerabilities should done. To evaluate security, this paper presents benchmarks specifically...

This article surveys the landscape of security verification approaches and techniques for computer systems at various levels: from a software-application level all way to physical hardware level. Different existing projects are compared, based on tools used aspects being examined. Since many require both software components work together provide system’s promised protections, it is not sufficient verify just levels or in mutually exclusive fashion. survey especially highlights system that...

The microarchitectural state held by predictors in modern processors can leak sensitive information. This is the first work to analyze security of a special type predictor, value and demonstrate new attacks. attacks bypass all existing predictor defenses which have not yet considered as sources vulnerabilities. further shows there are many attack variants, derived using our model. paper highlights importance analysis processor features before they realized silicon, so understood at design time.

Large Language Models (LLMs) have achieved remarkable success in various fields, but their training and finetuning require massive computation memory, necessitating parallelism which introduces heavy communication overheads. Driven by advances packaging, the chiplet architecture emerges as a potential solution, it can integrate computing power, well utilize on-package links with better signal integrity, higher bandwidth, lower energy consumption. However, most existing chiplet-related works...

Oblivious RAM (ORAM) hides the memory access patterns, enhancing data privacy by preventing attackers from discovering sensitive information based on sequence of accesses. The performance ORAM is often limited its inherent trade-off between security and efficiency, as concealing patterns imposes significant computational overhead. While prior works focus improving prefetching eliminating requests, we find that their very to workload locality behavior incurs additional management overhead...

Compute-in-memory (CiM) architecture is an emerging energy-efficient processing paradigm that has attracted widespread attention in AI and Internet of Things (IoT) applications. To protect statically stored sensitive data CiM, designers have implemented various hardware obfuscation techniques CiM architectures. However, we observe existing defense strategies are based on straightforward static-key deployment strategies, which pose vulnerabilities from the perspective key-pruning algorithms...

This paper implements the latest speech recognition technique and improves it so that can be used on embedded mobile devices. In order to implement system, I build two-layer Long Short-Term Memory networks (LSTMs) using TensorFlow framework train model by Mel Frequency Cepstral Coefficients (MFCCs) vector extracted from wave files. speeds up model, this innovatively applies pruning method LSTMs weights of each cell regularizing weight matrix regression layer. After pruning, retrain preserve...

This article reveals timing-based side-channel and covert-channel attacks from the translation look-aside buffers (TLBs) discusses how to design secure TLBs.

This paper mainly introduces the implementation of bank network design and system construction.In era rapid development, is becoming more important in daily life, especially some large facilities institutions, has become a necessary means to maintain its development.Because financial institution, needs are relatively high, not only be safe, efficient, convenient, but also consider fault tolerance data integrity.In terms demand, performance planning various aspects banking described point by...

The implications of ambimorphic archetypes have been far-reaching and pervasive. After years natural research into consistent hashing, we argue the simulation public-private key pairs, which embodies confirmed principles theory. Such a hypothesis might seem perverse but is derived from known results. Our focus in this paper not on whether well-known knowledge-based algorithm for emulation checksums by Herbert Simon runs Θ(n) time, rather exploring semantic tool harnessing telephony (Swale).

Timing-based side or covert channels in processor caches continue to present a threat computer systems, and they are the key many of recent Spectre Meltdown attacks. Based on improvements an existing three-step model for cache timing-based attacks, this work presents 88 Strong types theoretical vulnerabilities caches. To understand evaluate all possible caches, further implements new benchmark suite which can be used test attacks given design is vulnerable. In total, there 1094...