A reliable configuration for triggering a series string of power metal oxide semiconductor (MOS) devices without the use transformer coupling is presented. capacitor inserted between gate and ground each field effect transistor (MOSFET), except bottom MOSFET in stack. Using single input voltage signal to trigger MOSFET, division across network device capacitance capacitances triggers entire stack reliably. Design formulas are presented simple circuit protection discussed. Simulation shows...

The characteristics of a bipolar junction transistor operating in the avalanche region and then triggered into current mode second breakdown are formulated. If time BJT is subjected to secondary limited may be used as nanosecond, high voltage switch without sustaining damage. Several methods fast pulse generation, electrical optical, using this operation discussed. A 2000 V generator, 50 Ω, with risetime approximately 1 ns, jitter <100 ps, designed these results.

Theoretical and experimental results are presented for op-amp compensation using split-length transistors. By devices the right-half plane zero which plagues performance can be eliminated. Experimental indicate substantial enhancements in speed while reducing power consumption layout area. Further, these techniques used to compensate op-amps when small supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ).

From the Publisher: DRAM (Dynamic Random Access Memory) circuits are most manufactured integrated in production with annual sales of $25 billion. The future will bring embedding DRAM data processors for complete systems on a chip. This has increased number design engineers doing design. Circuit Design: A Tutorial teaches introductory-level memory chips. Topics covered include: Array, Peripheral Circuitry, Global Circuitry and Considerations, Voltage Converters, synchronization DRAMs.

As CMOS technology continues to evolve, the supply voltages are decreasing while at same time transistor threshold remaining relatively constant. Making matters worse, inherent gain available from nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by cascoding become less useful in nano-scale processes. Horizontal cascading (multi-stage) must be used order realize op-amps low voltage This paper discusses indirect compensation using split-length devices. A...

A low-cost and high-resolution capacitive-to-digital converter integrated circuit is used for droplet position detection in a digital microfluidic system. field-programmable gate array FPGA as the logic hub of system highly reliable efficient control circuit. fast-fabricating PCB (printed board) substrate proposed. Smaller actuation threshold voltages than those previously reported are obtained. Droplets (3 µL) actuated by using 200 V, 500 Hz modulating pulsed voltage. Droplet positions can...

This paper proposes an energy management model using system dynamics (SD) modeling approach. The time span of the extends from 2003 to 2030. Model was calibrated and used for evaluation six policy scenarios. Population, per capita electricity consumption, industrial sectors were identified as key components inputs predict future supply demand needs. Particular attention paid, in proposed model, individual total amounts carbon released into atmosphere. Finally, demonstrate usefulness it...

A reliable circuit configuration is described for stacking power metal–oxide semiconductor field effect transistors (MOSFETs). The resulting has a hold off voltage N times larger than single MOSFET, where the number of MOSFETs used. capability to switch higher voltages and thus greater amounts power, into 50 Ω load, in approximately same time as device realized. Design considerations are presented selecting MOSFET. Using design method presented, 1.4 kV pulse generator, Ω, with 2 ns rise...

This paper describes a register-controlled symmetrical delay-locked loop (RSDLL) for use in high-frequency double-data-rate DRAM. The RSDLL inserts an optimum delay between the clock input buffer and output buffer, making DRAM data change simultaneously with rising or falling edges of clock. is shown to be insensitive variations temperature, power-supply voltage, process after being fabricated 0.21 /spl mu/m CMOS technology. measured r.m.s. jitter below 50 ps when operating frequency range...

The beta multiplier voltage reference (BMVR) is discussed as a direct replacement for the bandgap in CMOS process especially when substrate current concern. Performance of BMVR with regard to temperature and variations covered. Experimental results from 2-micron MOSIS test chip indicate that can be tuned within 10 mV desired value while maintaining coefficient below 1000 ppm/C supply sensitivity under 50 mV/V.

This paper presents the design of CMOS op-amps using indirect feedback compensation technique. The results in much faster and low power op-amps, significant reduction layout size better supply noise rejection

An analog layout assistant (ALAS!) is presented that automatically generates common-centroid, interdigitated device pairs and passive components. The user inputs a minimum of input parameters has the ability to interactively alter program. program can be used in conjunction with any editor imports CalTech Intermediate Format (CIF) layouts platform technology independent.

As CMOS technology continues to evolve, the supply voltages are decreasing while at same time transistor threshold remaining relatively constant. Making matters worse, inherent gain available from nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by vertically stacking (i.e. cascoding) becomes less useful in nano-scale processes. Horizontal cascading (multi-stage) must be used order realize op-amps low voltage This paper discusses new design realization of...

Droplet actuation, merging, and splitting using controlled electro-wetting are implemented on the top of a standard printed circuit board (PCB) resulting in fast prototyping microfluidic platform for biological experiments. In system reported here PCB is used as substrate covered with Saran Wrap. The Wrap can then be coated, or not, commercial water repellent liquid. hydrophobic surface supporting dielectric layer Results show that lower actuation voltages frequencies achieved, than...

An insulated-gate bipolar transistor (IGBT) pulse generator for repetitive transcranial magnetic stimulation used in vivo laboratory experiments on small animals, such as mice, is reported. The based upon an IGBT that can switch 700 A of current 1 ms and has a DC breakdown voltage 1200 V. duration the design’s output controlled by, follows, input trigger pulse. amplitude pulses determined by external high-voltage power supply energy stored 330 µF capacitor bank. approach enables applied...

Series operation of power metal-oxide semiconductor field-effect transistors (MOSFETs) to increase their effective hold off voltage is described. The design procedure presented a modification recently reported [Baker and Johnson, Rev. Sci. Instrum. 63, 5799 (1992)] method. Comments are made on implementing MOSFET stacks in various types instrumentation.