In this study, we present the steep switching characteristics of bendable feedback field-effect transistors (FBFETs) consisting p(+)-i-n(+) Si nanowires (NWs) and dual-top-gate structures. As a result positive loop in intrinsic channel region, our FBFET features outstanding an on/off current ratio approximately 10(6), point subthreshold swings (SSs) 18-19 mV/dec n-channel operation mode 10-23 p-channel mode. Not only can these devices operate n- or modes, their also be modulated by adjusting...

In this study, we propose newly designed feedback field-effect transistors that utilize the positive of charge carriers in single-gated silicon channels to achieve steep switching behaviors. The band diagram, I-V characteristics, subthreshold swing, and on/off current ratio are analyzed using a commercial device simulator. Our proposed exhibit swings less than 0.1 mV dec-1, an approximately 1011, on-current 10-4 A at room temperature, demonstrating characteristics superior those other...

Abstract Memory hierarchy among conventional memory technologies is one of the main bottlenecks in modern computer systems; alternative are thus necessary for quasi‐nonvolatile applications. Herein, a fully complementary metal‐oxide‐semiconductor‐compatible composed p + ‐n‐p‐n silicon on silicon‐on‐insulator substrate presented. The device demonstrates high‐speed write capability ( ≤ 100 ns), long retention time (100 s), and nondestructive read (1000 with high sensing current margin ≈ 10 9 )...

In this paper, we propose a novel static random access memory (SRAM) unit cell design and its array structure consisting of single-gated feedback field-effect transistors (FBFETs). To verify the SRAM characteristics, basic operations write disturbances are investigated through mixed-mode technology computer-aided simulations. The exhibits superior characteristics including speed 0.6 ns, fast read-out ~0.1 retention time 3600 s. Furthermore, advantages in density, with small area 8F <sup...

Abstract The von Neumann architecture used as the basic operating principle in computers has a bottleneck owing to disparity between central processing unit and memory access speeds, which leads high power consumption speed reduction, reducing overall system performance. However, feedback field-effect transistors (FBFETs) have attracted significant attention their potential realize next-generation electronic devices based on switching characteristics. Therefore, this study, we configured...

Abstract Silicon field-effect diodes (FEDs) have attracted considerable attention owing to their wide range of applications. However, the proposed silicon FEDs been primarily implemented using silicon-on-insulator (SOI) technology because forward-bias leakage path in bulk substrates. In this study, we demonstrated a FED with p+-n-p-n+ structure fabricated on substrate. The FED—which used conventional complementary metal-oxide–semiconductor (CMOS) process—exhibited excellent electrical...

In this article, we propose an integrate-and-fire (IF) neuron circuit using a single-gated silicon nanowire feedback field-effect transistor that utilizes positive loop. The IF operations are investigated through mixed-mode technology computer-aided design simulations. composed of four component transistors (plus one capacitor) exhibits high firing frequency ~20 kHz and low power energy consumption 7 μW 2.9 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

In this work, we report a fully CMOS-compatible single silicon neuron device, by exploiting interlinked positive and negative feedback loops. The device exhibits the key features of leaky integrate-and-fire functionality can produce neuronal oscillations that resemble biological oscillations. stochastic nature analog input-sensitivity switching dynamics are observed in device. Moreover, two-terminal do not require any power supplied external bias lines.

Abstract In this study, we demonstrate the static random access memory (SRAM) characteristics generated by weak impact ionization in bendable field-effect transistors (FETs) with n + -p-n silicon nanowire (SiNW) channels. Our SiNW FETs show not only superior switching such as an on/off current ratio of ~10 5 and steep subthreshold swing (~5 mV/dec) but also reliable SRAM characteristics. The originate from positive feedback loops ionization. This paper describes detail operating mechanism...

We demonstrate the nonvolatile and volatile memory characteristics of a gate-all-around silicon nanowire feedback field-effect transistor (FBFET) with nitride charge-storage layer analyzed by commercial TCAD simulator. Our FBFET exhibits threshold voltage window 0.76 V programming/erasing time 1 μs in mode. investigated delay read operations accumulated charges intrinsic channel region this Moreover, sensing margin 6.3 μA read/write speed 10 ns an outstanding retention time, as well...

In this article, we present a transposable three-transistor static random access memory (3T-SRAM) array consisting of independent double-gate feedback fieldeffect transistors as binary synaptic devices and transistors. The functions the 2 × SRAM are investigated-through mixed-mode technology computeraided design simulations. This 3T-SRAM provides parallel bidirectional updates with fast operating speed. Furthermore, simplified spike-timing-dependent plasticity learning rule is implemented by...

In this paper, we propose inverting logic-in-memory (LIM) cells comprising silicon nanowire feedback field-effect transistors with steep switching and holding characteristics. The timing diagrams of the proposed LIM under dynamic static conditions are investigated via mixed-mode technology computer-aided design simulation to verify performance. have an operating speed order nanoseconds, ultra-high voltage gain, a longer retention time than that conventional random access memory. disturbance...

In this study, we propose an integrate-and-fire (I&amp;amp;F) neuron circuit using a p-n - diode that utilizes latch-up phenomenon and investigate the I&amp;amp;F operation without external bias voltages mixed-mode technology computer-aided design (TCAD) simulations. The composed of one p-n-p-n diode, three MOSFETs, capacitor operates with no lines, its has energy consumption 0.59 fJ efficiency 96.3% per spike. presented is superior in terms structural simplicity, number comparison...

Abstract The switchable‐memory operation of a feedback silicon nanowire transistor with dual‐gate structure is demonstrated. single exhibits volatile memory characteristics retention time longer than 3600 s, as well switching capability subthreshold swing lower 7 mV dec −1 . A gate‐controlled window forms around gate voltage 0 V owing to the positive loop in channel region, allowing program/erase endurance more 1000 cycles. transistor, capability, opens up possibility overcoming not only...

Abstract In this paper, a novel reconfigurable logic‐in‐memory built using silicon transistors is proposed. The transistor can be reconfigured as p ‐ or n ‐switchable memory by controlling the polarity of gate inputs. These electrical characteristics are enabled utilizing holes electrons majority charge carriers for positive feedback loop. functions NOT and YES gates with same cell comprising load resistor demonstrated. Moreover, it revealed that two‐input cell, based on two resistor,...

In this study, we propose doping-less feedback field-effect transistors (DLFBFETs). Our DLFBFETs are 5 nm thick intrinsic semiconductor bodies with dual gates. Usually, virtually doped through charge plasma phenomena caused by the source, drain, and dual-gate electrodes as well gate biases. can be fabricated a simple process of creating contact between metal silicon body without any doping processes. The voltages applied to both gates determine whether operate in diode or transistor (FBFET)...

In this paper, we propose a doping- and capacitor-less 1T-DRAM cell, which achieved virtual doping by leveraging charge plasma bias-induced electrostatic (bias-ED) techniques in 5 nm-thick intrinsic silicon body, thereby eliminating processes. Platinum was contact with the drain, while aluminum source, enabling of body into

In this paper, we demonstrate nondestructive readout memory characteristics of a bistable resistor (biristor) with an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -p-n Si nanowire (SiNW) channel on bendable substrate. The SiNW is fabricated using top-down route, which compatible the current complementary metal-oxide-semiconductor technology. biristor shows outstanding such as retention time 10 s and sensing margin ~23-μA at room...

In this study, we present a reconfigurable feedback field-effect transistor (FET) that can operate in both p- and n-type configurations using mechanism. contrast to previously reported FETs, our device utilizes single gate trigger mechanism at the center, resulting steep switching characteristics. The exhibited high symmetry of transfer characteristics, an on/off current ratio approximately 1010, extremely low subthreshold swings, on-current 1.5 mA voltages configurations. addition, because...

In this paper, we describe the feedback and tunneling operations of a dual top gate field-effect transistor (FET) with p +-i-n + doped silicon nanowire channel. The functions selectively in either FET (FBFET) or mode by modulating source-to-drain voltage, it features an outstanding subthreshold swing characteristic 6.15 mV dec-1 on/off current ratio (I on/I off) approximately 106 operating 41.3 I off ∼107 mode. Moreover, our device FBFET operation has memory characteristics retention time...