Time series motifs have been in the literature for about fifteen years, but only recently begun to receive significant attention research community. This is perhaps due growing realization that they implicitly offer solutions a host of time problems, including rule discovery, anomaly detection, density estimation, semantic segmentation, etc. Recent work has improved scalability point where exact can be computed on datasets with up million data points tenable time. However, some domains,...

Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve quality designs. This is reason why theoretical lower bounds on delay and area an adder have been analysed, circuits with close to these designed. In this paper, we present a novel design that exponentially faster than traditional adders; however, it produces incorrect results, deterministically, for very small fraction input combinations. We also constructed reliable version...

Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve quality designs. This is reason why theoretical lower bounds on delay and area an adder have been analysed, circuits with close to these designed. In this paper, we present a novel design that exponentially faster than traditional adders; however, it produces incorrect results, deterministically, for very small fraction input combinations. We also constructed reliable version...

In cryptography, side channel attacks, such as power analysis, attempt to uncover secret information from the physical implementation of cryptosystems rather than exploiting weaknesses in cryptographic algorithms themselves. The design and physically secure is a challenge for both hardware software designers. Measuring evaluating security system manual empirical, which costly time consuming; this work demonstrates that it possible automate these processes. We introduce systematic methodology...

Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these produce hardware that is larger than necessary, as they do not allow instructions share resources. This study presents an efficient heuristic which transforms a set custom into single datapath on can execute. Our approach based the classic problems finding longest common subsequence substring two (or more)...

Since the inception of digital microfluidics, synthesis problems scheduling, placement and routing have been performed offline (before runtime) due to their algorithmic complexity. However, with increasing maturity microfluidic research, online is becoming a realistic possibility that can bring new benefits in areas dynamic control-flow, fault-tolerance live-feedback. This paper contributes process by introducing fast, novel path-based scheduling algorithm produces better schedules than list...

We introduce an online synthesis flow for digital microfluidic biochips, which will enable real-time response to errors and control flow. The objective of this is facilitate fast assay while minimally compromising the quality results. In particular, we show that a virtual topology, constrains allowable locations operations such as mixing, dilution, sensing, etc., in lieu traditional placement, can significantly speed up process without lengthening execution time.

We introduce an online synthesis flow, focusing primarily on the virtual topology and operation binder, for digital microfluidic biochips, which will enable real-time response to errors control flow. The objective of this flow is facilitate fast assay while minimally compromising quality results. In particular, we show that a topology, constrains allowable locations operations such as mixing, dilution, sensing, etc., in lieu traditional placement, can significantly speed up process without...

In this work we created functional microfluidic chips without actually designing them. We accomplished by first generating a library of thousands different random chip designs, then simulating the behavior each design on computer using automated finite element analysis. The simulation results were saved to database which user can query via find designs suitable for specific task. To demonstrate functionality, used our select that generate any three desired concentrations solute. also...

The ability to thoroughly mix two fluids is a fundamental need in microfluidics. While variety of different microfluidic mixers have been designed by researchers, it remains unknown which (if any) these are optimal (that is, designs provide the most thorough mixing with smallest possible fluidic resistance across mixer). In this work, we automatically and rationally optimized mixer. We accomplished first generating library thousands randomly mixers, then using non-dominated sorting genetic...

The discovery of conserved (repeated) patterns in time series is arguably the most important primitive data mining. Called motifs, these are useful their own right, and also used as inputs into classification, clustering, segmentation, visualization, anomaly detection algorithms. Recently Matrix Profile has emerged a promising representation to allow efficient exact computation top-k motifs series. State-of-the-art algorithms for computing fast enough many tasks. However, handful domains,...

The increasing demand for complex and specialized embedded hardware must be met by processors which are optimized performance, yet also extremely flexible. In our work, we explore the tradeoff between flexibility performance in domain of reconfigurable processor design. Specifically, seek to identify regularly occurring, computation-heavy patterns an application or set applications. These become candidates hard-logic implementation, potentially flexible fabric as special instructions. this...

As digital microfluidic biochips (DMFBs) have matured over the last decade, efforts been made to 1.) reduce cost, and 2.) produce general-purpose chips. While work done generalize DMFBs typically depends on flexibility of individually controlled electrodes, such devices high wiring complexity, which requires costly multi-layer printed circuit boards (PCBs). In contrast, pin-constrained but droplet coordination. We present a field-programmable DMFB that leverages cost-savings designs, is...

CPUs and dedicated accelerators (namely GPUs FPGAs) continue to grow increasingly large complex support todays demanding performance power requirements. Designers are tasked with evaluating the of similarly design spaces during pre-silicon for reduce time-to-market limit manufacturing costs, or figure out how best map applications onto FPGAs using high-level synthesis tools. Typically, cycle-accurate simulators used evaluate workloads avoid overhead place-and-route when targeting FPGAs;...

Pneumatically-actuated soft robots have advantages over traditional rigid in many applications. In particular, their flexible bodies and gentle air-powered movements make them more suitable for use around humans other objects that could be injured or damaged by robots. However, existing systems controlling currently require dedicated electromechanical hardware (usually solenoid valves) to maintain the actuation state (expanded contracted) of each independent actuator. When combined with...

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FPGA performance is currently lacking for arithmetic circuits. Large sums of k > 2 integer values a computationally intensive operation in applications such as digital signal and video processing. In ASIC design, compressor trees, Wallace Dadda are used parallel accumulation; however, the LUT structure fast carry-chains employed by modern FPGAs favor trees carry-propagate adders (CPAs), which poor choice design. This paper presents first method to successfully synthesize on LUT-based FPGAs....

Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The bypass the general routing network and are embedded in logic blocks FPGAs for fast addition. Conventional intuition that such can be used only implementing carry-propagate addition; state-of-the-art FPGA synthesizers exploit these specific circuits. This paper demonstrates to build compressor trees, i.e., multi-input addition circuits parallel accumulation partial product reduction multipliers...

Compressor trees are a class of circuits that generalizes multioperand addition and the partial product reduction parallel multipliers using carry-save arithmetic. naturally occur in many DSP applications, such as FIR filters, and, more general case, their use can be maximized through application high-level transformations to arithmetically intensive data flow graphs. Due presence carry-chains, it has long been thought 2- or 3-input carry-propagate adders efficient than compressor for FPGA...

Synthesis of digital microfluidic biochips (DMFBs) is a crucial to the advancement and realization miniaturized, automated, programmable biochemistry solutions; synthesis performed in three steps: scheduling, placement routing. In principle, algorithms for specific steps should be interchangeable with one another; however, different research groups typically develop each step isolation from another. Thus, it difficult compare against another, or determine which share synergies. We introduce...

We introduce a compiler that automatically inserts software countermeasures to protect cryptographic algorithms against power-based side-channel attacks. The first estimates which instruction instances leak the most information through side-channels. This is obtained either by dynamic analysis, evaluating an theoretic metric over power traces acquired during execution of input program, or static analysis. As leakage implies loss security, then identifies (groups of) with countermeasure such...

We have implemented an FPGA routing algorithm on a shared memory multi-processor using the Galois API, which offers speculative parallelism in software. The router is parallel implementation of PathFinder, basis for most commercial routers. parallelize maze expansion step each net, while nets sequentially to limit amount rollback that would likely occur due misspeculation. Our relies non-blocking priority queues, use software transactional (SMT), identify best route net. experimental results...