Qinghang Zhao

ORCID: 0000-0003-0116-8975
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About
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Research Areas
  • Thin-Film Transistor Technologies
  • Advancements in Semiconductor Devices and Circuit Design
  • Advanced Memory and Neural Computing
  • Energy Harvesting in Wireless Networks
  • Semiconductor materials and devices
  • Advanced Battery Technologies Research
  • Organic Electronics and Photovoltaics
  • Advanced Neural Network Applications
  • Machine Learning and ELM
  • Industrial Vision Systems and Defect Detection
  • CCD and CMOS Imaging Sensors
  • Advanced Optical Sensing Technologies
  • Smart Grid and Power Systems
  • Advancements in Battery Materials
  • Analog and Mixed-Signal Circuit Design
  • Neuroscience and Neural Engineering
  • Advanced Sensor and Energy Harvesting Materials
  • Human Pose and Action Recognition
  • Nanowire Synthesis and Applications
  • Innovative Energy Harvesting Technologies
  • Low-power high-performance VLSI design
  • Power Line Communications and Noise
  • Advanced Image Processing Techniques
  • High-Voltage Power Transmission Systems
  • Random lasers and scattering media

Xidian University
2022-2025

Hikvision (China)
2020

Tsinghua University
2015-2018

10.1145/3658617.3697590 article EN Proceedings of the 28th Asia and South Pacific Design Automation Conference 2025-01-20

10.1109/icassp49660.2025.10889195 article EN ICASSP 2022 - 2022 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) 2025-03-12

Thin-film transistors (TFT) in hydrogenated amorphous silicon, metal oxide, and small molecule polymer organic semiconductors would all hold promise as potential device candidates to large area flexible electronics applications. A universal compact dc model was developed with a proper balance between the physical mathematical approaches for these thin-film (TFTs). It can capture common key parameters used performance benchmarking of different TFTs while being applicable wide range TFT...

10.1109/ted.2017.2655110 article EN IEEE Transactions on Electron Devices 2017-02-14

Nonvolatile static random access memory (nvSRAM) has been widely investigated as a promising on-chip architecture in energy harvesting sensor nodes, due to zero standby power, resilience power failures, and fast read/write operations. However, conventional approaches back up all data from into nonvolatile when failures happen. It leads significant overhead peak inrush current, which negative impact on the system performance circuit reliability. This paper proposes holistic backup...

10.1109/tcad.2017.2648841 article EN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2017-01-05

In modern energy harvesting sensor nodes, nonvolatile SRAM (nvSRAM) has been widely investigated as a promising on-chip memory architecture because of its zero standby power, resilience to power failures, and fast read/write operations. However, conventional approaches transfer all data from into NVM during the backup process. Thus, large storage capacitors are normally required. addition, high peak inrush current is generated instantaneously, which negative impact on efficiency circuit...

10.7873/date.2015.0357 article EN Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 2015-01-01

In modern energy harvesting sensor nodes, nonvolatile SRAM (nvSRAM) has been widely investigated as a promising on-chip memory architecture because of its zero standby power, resilience to power failures, and fast read/write operations. However, conventional approaches transfer all data from into NVM during the backup process. Thus, large storage capacitors are normally required. addition, high peak inrush current is generated instantaneously, which negative impact on efficiency circuit...

10.5555/2755753.2755756 article EN Design, Automation, and Test in Europe 2015-03-09

As a practical approach for compressing convolutional neural networks (CNNs), network pruning has been rapidly developed in recent years. The conventional methods prune inactive filters permanently from models to reduce the width of each layer and then train pruned model until convergence. However, such have limitations that: (1) activation-based criteria ignore correlation between filters, leading attenuation types features; (2) permanent filter removal restricts architecture subsequent...

10.1109/tcsvt.2022.3216101 article EN IEEE Transactions on Circuits and Systems for Video Technology 2022-11-03

The flexible electronics is promising in the area of Internet Things and wearable devices thin-film transistor (TFT) technologies are crucial for electronics. Among them, zero-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> load TFT circuits widely used its simple structure high gain merits. However, yield model lacking circuits. In this paper, analytical noise margin NAND gate NOR derived. Based on that, a simple, accurate, highly...

10.1109/ted.2015.2506722 article EN IEEE Transactions on Electron Devices 2016-01-06

Flexible electronics based on thin-film transistors (TFTs) are promising in the area of Internet Things and wearable devices, where pseudo-CMOS logic is widely used unipolar TFT circuits. Though plenty device models exist, analytical circuit-level still absent, preventing further development design analysis flexible In this paper, we derive noise margin (NM), delay, power for Furthermore, simplify those manual optimization. All validated by SPICE simulations, model its parameters extracted...

10.1109/ted.2017.2695527 article EN IEEE Transactions on Electron Devices 2017-06-01

Flexible electronic is a promising technology for flexible and large-area sensing IoT applications, where ADC fundamental component This paper proposes configurable VCO-based ADC, implemented with Oxide Thin-Film Transistors(TFT) technology. A VCO four connecting modes designed to configure the working under different power resolutions. An Inkjet printing interconnection introduced enable configurability of even after all TFT transistors are fabricated. It allows be customized applications...

10.1109/iscas.2017.8050682 article EN 2022 IEEE International Symposium on Circuits and Systems (ISCAS) 2017-05-01

Image deblurring based only on the blurry image is challenging as motion information lost while imaging. Event cameras capture texture of moving objects in high temporal resolution with asynchronous events. In this paper, we extract features from events and fuse them background for event-based deblurring. Spiking neural network (SNN), a widely recognized event feature extractor, well suited extraction due to its resolution. However, extracting exclusively SNN challenging. We propose novel...

10.1109/tcsvt.2023.3317976 article EN IEEE Transactions on Circuits and Systems for Video Technology 2023-09-21

Thin-film transistor (TFT) circuits are important for flexible electronics which promising in the area of wearable devices. However, most TFT technologies only have unipolar devices and process variation defective rate relatively high, impose challenges to circuit design. In this paper, we propose a novel logic array based on pseudo-CMOS address problem A multi-layer interconnect architecture wire routing methodology presented improve routability meanwhile efficiency. The experimental...

10.1145/3061639.3062227 article EN 2017-06-13

Dynamic vision sensor (DVS) is novel neuromorphic imaging device that generates asynchronous events. Despite the high temporal resolution and dynamic range features, DVS faced with background noise problem. Spatiotemporal filter an effective hardware-friendly solution for denoising but previous designs have large memory overhead or degraded performance issues. In this paper, we present a lightweight real-time spatiotemporal set-associative cache-like memories, which has low space complexity...

10.1145/3676536.3676710 preprint EN 2024-10-27

Thin-film transistor (TFT) circuits are important for flexible electronics which promising in the area of wearable devices and Internet Things. However, most TFT technologies only have unipolar process variation defective rate relatively high, impose challenges to circuit design. In this paper, we propose a novel logic array design based on pseudo-CMOS address problems A multilayer interconnection architecture is presented improve routability efficiency. Cell mapping wire routing algorithms,...

10.1109/tcad.2018.2878185 article EN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2018-10-25

Thin-film transistor (TFT) circuits are facing the challenges of unipolar device, process variation, and yield problems, which can be addressed by pseudo-CMOS logic array with multi-layer interconnect. However, existing design methodology does not take mechanical strain temperature into consideration may seriously affect carrier mobility TFT thus performance whole circuits. This paper presents a novel cell mapping algorithm including intrarow step inter-row for flexible to mitigate...

10.5555/3201607.3201756 article EN Asia and South Pacific Design Automation Conference 2018-01-22

Thin-film transistor (TFT) circuits are facing the challenges of unipolar device, process variation, and yield problems, which can be addressed by pseudo-CMOS logic array with multi-layer interconnect. However, existing design methodology does not take mechanical strain temperature into consideration may seriously affect carrier mobility TFT thus performance whole circuits. This paper presents a novel cell mapping algorithm including intrarow step inter-row for flexible to mitigate...

10.1109/aspdac.2018.8297395 article EN 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) 2018-01-01

Flexible capacitive pressure sensing system (FCPSS) is promising in the area of healthcare, robotics, and Internet Things (IoT). As size array increases, designing energy-efficient FCPSS getting challenging. This work provides a comprehensive solution for low-power design, where major contributions are as follows. 1) Crosstalk-induced measurement error crossbar structure first studied an accurate linear iterative algorithm proposed on-chip calibration (SAC). 2) Binary Neural Network...

10.1109/iscas45731.2020.9181209 article EN 2022 IEEE International Symposium on Circuits and Systems (ISCAS) 2020-09-29

Despite the large noise margin merit of pseudo- CMOS logic, its analytical model is absent. In this paper, we derive static for pseudo-CMOS (pseudo- D) logic circuits. Finally, analyze impact design parameters on margin. Simulations show modeling error about 3%.

10.1109/cad-tft.2016.7785043 article EN 2016-10-01
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